x86, UV: Correct UV2 BAU destination timeout
Correct the UV2 broacast assist unit's destination timeout period. And the activation status register in UV2 should be tested for a destination timeout with a 4, not a 2. The values for Active versus Timeout were reversed. This patch is critical for TLB shootdown on an Altix UV2 system (i.e. the follow-on to the current Altix UV). Destination timeout period: The period is set in 4 bits of memory-mapped register MISC_CONTROL. The left bit toggles base period between 10us and 80us. The other 3 bits are the multiplier. Decimal 15, hex f, gives the maximum: 7 * 80us Signed-off-by: Cliff Wickman <cpw@sgi.com> Link: http://lkml.kernel.org/r/20110621122243.117324443@sgi.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -67,7 +67,7 @@
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* we're using 655us, similar to UV1: 65 units of 10us
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*/
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#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
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#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL)
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#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
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#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
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UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
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@ -106,12 +106,20 @@
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#define DS_SOURCE_TIMEOUT 3
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/*
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* bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
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* values 1 and 5 will not occur
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* values 1 and 3 will not occur
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* Decoded meaning ERROR BUSY AUX ERR
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* ------------------------------- ---- ----- -------
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* IDLE 0 0 0
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* BUSY (active) 0 1 0
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* SW Ack Timeout (destination) 1 0 0
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* SW Ack INTD rejected (strong NACK) 1 0 1
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* Source Side Time Out Detected 1 1 0
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* Destination Side PUT Failed 1 1 1
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*/
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#define UV2H_DESC_IDLE 0
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#define UV2H_DESC_DEST_TIMEOUT 2
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#define UV2H_DESC_DEST_STRONG_NACK 3
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#define UV2H_DESC_BUSY 4
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#define UV2H_DESC_BUSY 2
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#define UV2H_DESC_DEST_TIMEOUT 4
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#define UV2H_DESC_DEST_STRONG_NACK 5
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#define UV2H_DESC_SOURCE_TIMEOUT 6
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#define UV2H_DESC_DEST_PUT_ERR 7
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