drm/amdgpu: fix aper_base for APU
[Why] Wrong fb offset results in dmub f/w errors and white screen. [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 [How] Read aper_base from mmhub because GC is off by default v2: use BAR for passthrough (Alex) Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -638,6 +638,12 @@ static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
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adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
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adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
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#ifdef CONFIG_X86_64
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if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
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adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev);
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adev->gmc.aper_size = adev->gmc.real_vram_size;
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}
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#endif
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/* In case the PCI BAR is larger than the actual amount of vram */
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adev->gmc.visible_vram_size = adev->gmc.aper_size;
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if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
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