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drm/bridge: tc358767: Split tc_set_video_mode() into common and (e)DP part

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The tc_set_video_mode() sets up both common and (e)DP video mode settings of
the bridge chip. Split the function into tc_set_common_video_mode() to set
the common settings and tc_set_edp_video_mode() to set the (e)DP specific
settings. No functional change.

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Lucas Stach <l.stach@pengutronix.de> # In both DPI to eDP and DSI to DPI mode.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Maxime Ripard <maxime@cerno.tech>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220329085015.39159-11-marex@denx.de
This commit is contained in:
Marek Vasut 2022-03-29 10:50:14 +02:00 committed by Robert Foss
parent 71f7d9c031
commit aebe58a7af
No known key found for this signature in database
GPG Key ID: 3EFD900F76D1D784
1 changed files with 38 additions and 27 deletions
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65
drivers/gpu/drm/bridge/tc358767.c
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@ -734,33 +734,16 @@ err_dpcd_read:
return ret;
}
static int tc_set_video_mode(struct tc_data *tc,
const struct drm_display_mode *mode)
static int tc_set_common_video_mode(struct tc_data *tc,
const struct drm_display_mode *mode)
{
int ret;
int vid_sync_dly;
int max_tu_symbol;
int left_margin = mode->htotal - mode->hsync_end;
int right_margin = mode->hsync_start - mode->hdisplay;
int hsync_len = mode->hsync_end - mode->hsync_start;
int upper_margin = mode->vtotal - mode->vsync_end;
int lower_margin = mode->vsync_start - mode->vdisplay;
int vsync_len = mode->vsync_end - mode->vsync_start;
u32 dp0_syncval;
u32 bits_per_pixel = 24;
u32 in_bw, out_bw;
/*
* Recommended maximum number of symbols transferred in a transfer unit:
* DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
* (output active video bandwidth in bytes))
* Must be less than tu_size.
*/
in_bw = mode->clock * bits_per_pixel / 8;
out_bw = tc->link.num_lanes * tc->link.rate;
max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
int ret;
dev_dbg(tc->dev, "set mode %dx%d\n",
mode->hdisplay, mode->vdisplay);
@ -818,8 +801,35 @@ static int tc_set_video_mode(struct tc_data *tc,
FIELD_PREP(COLOR_B, 99) |
ENI2CFILTER |
FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
if (ret)
return ret;
return ret;
}
static int tc_set_edp_video_mode(struct tc_data *tc,
const struct drm_display_mode *mode)
{
int ret;
int vid_sync_dly;
int max_tu_symbol;
int left_margin = mode->htotal - mode->hsync_end;
int hsync_len = mode->hsync_end - mode->hsync_start;
int upper_margin = mode->vtotal - mode->vsync_end;
int vsync_len = mode->vsync_end - mode->vsync_start;
u32 dp0_syncval;
u32 bits_per_pixel = 24;
u32 in_bw, out_bw;
/*
* Recommended maximum number of symbols transferred in a transfer unit:
* DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
* (output active video bandwidth in bytes))
* Must be less than tu_size.
*/
in_bw = mode->clock * bits_per_pixel / 8;
out_bw = tc->link.num_lanes * tc->link.rate;
max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
/* DP Main Stream Attributes */
vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
@ -869,10 +879,7 @@ static int tc_set_video_mode(struct tc_data *tc,
FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
BPC_8);
if (ret)
return ret;
return 0;
return ret;
}
static int tc_wait_link_training(struct tc_data *tc)
@ -1185,7 +1192,11 @@ static int tc_edp_stream_enable(struct tc_data *tc)
return ret;
}
ret = tc_set_video_mode(tc, &tc->mode);
ret = tc_set_common_video_mode(tc, &tc->mode);
if (ret)
return ret;
ret = tc_set_edp_video_mode(tc, &tc->mode);
if (ret)
return ret;