arm64: dts: ti: k3-j721e-main: Update delay select values for MMC subsystems
Update the delay values for various speed modes supported, based on the revised august 2021 J721E Datasheet. [1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in https://www.ti.com/lit/ds/symlink/tda4vm.pdf, (SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021) Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20230424093827.1378602-1-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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@ -1287,8 +1287,8 @@
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bus-width = <8>;
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mmc-hs200-1_8v;
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mmc-ddr-1_8v;
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ti,otap-del-sel-legacy = <0xf>;
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ti,otap-del-sel-mmc-hs = <0xf>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-ddr52 = <0x5>;
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ti,otap-del-sel-hs200 = <0x6>;
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ti,otap-del-sel-hs400 = <0x0>;
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@ -1309,11 +1309,12 @@
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assigned-clocks = <&k3_clks 92 0>;
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assigned-clock-parents = <&k3_clks 92 1>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-sd-hs = <0xf>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0xf>;
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ti,otap-del-sel-sdr25 = <0xf>;
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ti,otap-del-sel-sdr50 = <0xc>;
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ti,otap-del-sel-ddr50 = <0xc>;
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ti,otap-del-sel-sdr104 = <0x5>;
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ti,itap-del-sel-legacy = <0x0>;
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ti,itap-del-sel-sd-hs = <0x0>;
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ti,itap-del-sel-sdr12 = <0x0>;
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@ -1335,11 +1336,12 @@
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assigned-clocks = <&k3_clks 93 0>;
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assigned-clock-parents = <&k3_clks 93 1>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-sd-hs = <0xf>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0xf>;
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ti,otap-del-sel-sdr25 = <0xf>;
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ti,otap-del-sel-sdr50 = <0xc>;
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ti,otap-del-sel-ddr50 = <0xc>;
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ti,otap-del-sel-sdr104 = <0x5>;
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ti,itap-del-sel-legacy = <0x0>;
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ti,itap-del-sel-sd-hs = <0x0>;
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ti,itap-del-sel-sdr12 = <0x0>;
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