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drm/amdgpu/smu11.0: convert to IP version checking

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Use IP versions rather than asic_type to differentiate
IP version specific features.

v2: rebase

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2021-07-27 17:28:00 -04:00
parent a8967967f6
commit af3b89d3a6
1 changed files with 46 additions and 42 deletions
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88
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
View File

@ -90,36 +90,37 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
struct amdgpu_firmware_info *ucode = NULL;
if (amdgpu_sriov_vf(adev) &&
((adev->asic_type == CHIP_NAVI12) ||
(adev->asic_type == CHIP_SIENNA_CICHLID)))
((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
(adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7))))
return 0;
switch (adev->asic_type) {
case CHIP_ARCTURUS:
chip_name = "arcturus";
break;
case CHIP_NAVI10:
switch (adev->ip_versions[MP1_HWIP]) {
case IP_VERSION(11, 0, 0):
chip_name = "navi10";
break;
case CHIP_NAVI14:
case IP_VERSION(11, 0, 5):
chip_name = "navi14";
break;
case CHIP_NAVI12:
case IP_VERSION(11, 0, 9):
chip_name = "navi12";
break;
case CHIP_SIENNA_CICHLID:
case IP_VERSION(11, 0, 7):
chip_name = "sienna_cichlid";
break;
case CHIP_NAVY_FLOUNDER:
case IP_VERSION(11, 0, 11):
chip_name = "navy_flounder";
break;
case CHIP_DIMGREY_CAVEFISH:
case IP_VERSION(11, 0, 12):
chip_name = "dimgrey_cavefish";
break;
case CHIP_BEIGE_GOBY:
case IP_VERSION(11, 0, 13):
chip_name = "beige_goby";
break;
default:
if (adev->asic_type == CHIP_ARCTURUS) {
chip_name = "arcturus";
break;
}
dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
return -EINVAL;
}
@ -238,38 +239,39 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
if (smu->is_apu)
adev->pm.fw_version = smu_version;
switch (smu->adev->asic_type) {
case CHIP_ARCTURUS:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
break;
case CHIP_NAVI10:
switch (adev->ip_versions[MP1_HWIP]) {
case IP_VERSION(11, 0, 0):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
break;
case CHIP_NAVI12:
case IP_VERSION(11, 0, 9):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
break;
case CHIP_NAVI14:
case IP_VERSION(11, 0, 5):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
break;
case CHIP_SIENNA_CICHLID:
case IP_VERSION(11, 0, 7):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
break;
case CHIP_NAVY_FLOUNDER:
case IP_VERSION(11, 0, 11):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
break;
case CHIP_VANGOGH:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
break;
case CHIP_DIMGREY_CAVEFISH:
case IP_VERSION(11, 0, 12):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
break;
case CHIP_BEIGE_GOBY:
case IP_VERSION(11, 0, 13):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
break;
case CHIP_CYAN_SKILLFISH:
case IP_VERSION(11, 0, 8):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
break;
default:
if (adev->asic_type == CHIP_ARCTURUS) {
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
break;
}
dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
break;
@ -492,8 +494,9 @@ int smu_v11_0_fini_smc_tables(struct smu_context *smu)
int smu_v11_0_init_power(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
struct smu_power_context *smu_power = &smu->smu_power;
size_t size = smu->adev->asic_type == CHIP_VANGOGH ?
size_t size = adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ?
sizeof(struct smu_11_5_power_context) :
sizeof(struct smu_11_0_power_context);
@ -750,8 +753,9 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
/* Navy_Flounder/Dimgrey_Cavefish do not support to change
* display num currently
*/
if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
adev->asic_type <= CHIP_BEIGE_GOBY)
if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11) ||
adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ||
adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
return 0;
return smu_cmn_send_smc_msg_with_param(smu,
@ -1136,15 +1140,15 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
int ret = 0;
struct amdgpu_device *adev = smu->adev;
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
case CHIP_VANGOGH:
switch (adev->ip_versions[MP1_HWIP]) {
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 5):
case IP_VERSION(11, 0, 9):
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 11):
case IP_VERSION(11, 0, 12):
case IP_VERSION(11, 0, 13):
case IP_VERSION(11, 5, 0):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
if (enable)
@ -1630,11 +1634,11 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
mutex_lock(&smu_baco->mutex);
if (state == SMU_BACO_STATE_ENTER) {
switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
switch (adev->ip_versions[MP1_HWIP]) {
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 11):
case IP_VERSION(11, 0, 12):
case IP_VERSION(11, 0, 13):
if (amdgpu_runtime_pm == 2)
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_EnterBaco,