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TI K3 device tree updates for v6.5

Browse Source 
New Boards:
 phyBOARD-Lyra-AM625 Board support
 Toradex Verdin AM62 COM, carrier and dev boards
 
 New features:
 Across K3 SoCs:
  - Error Signaling Module(ESM) and Secproxy IPC modules
  - On board I2C EEPROM
  - Voltage Temp Monitoring (VTM) module
  - DM timers (GP Timers)
 J784s4:
  - R5 and C7x DSP remoteproc, ADC, QSPI
 AM69:
  - Addition of more peripherals: CPSW, eMMC, UARTs, I2C et al
 J721s2:
  - USB, Serdes, OSPI, PCIe
 AM62a:
 - Watchdog
 J721e:
 - HyperFlash/HyperBus
 AM62:
 - Type-C USB0 port
 
 Cleanups and non-urgent fixes
 Particularly large set of cleanups to get rid of dtbs_check errors and
 dtc warnings:
  - Addition of missing pinmux and uart nodes for AM64, AM62x, AM62A,
    J721e, J7200 that are used by bootloader
  - Split Pinmux regions/range to avoid holes for J721s2, J7200, J784s4
  - Drop bootargs and unneeded aliases across all K3 SoCs
  - Move aliases to board dts files from SoC dtsi files
  - Move to generic node name for can, rtc nodes on am65
  - s/-pins-default/default-pins/ to match upcoming pinctrl.yaml update
  - Fix pinctrl phandle references to use <> as separator where multiple
    entries are present
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Merge tag 'ti-k3-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt

TI K3 device tree updates for v6.5

New Boards:
phyBOARD-Lyra-AM625 Board support
Toradex Verdin AM62 COM, carrier and dev boards

New features:
Across K3 SoCs:
 - Error Signaling Module(ESM) and Secproxy IPC modules
 - On board I2C EEPROM
 - Voltage Temp Monitoring (VTM) module
 - DM timers (GP Timers)
J784s4:
 - R5 and C7x DSP remoteproc, ADC, QSPI
AM69:
 - Addition of more peripherals: CPSW, eMMC, UARTs, I2C et al
J721s2:
 - USB, Serdes, OSPI, PCIe
AM62a:
- Watchdog
J721e:
- HyperFlash/HyperBus
AM62:
- Type-C USB0 port

Cleanups and non-urgent fixes
Particularly large set of cleanups to get rid of dtbs_check errors and
dtc warnings:
 - Addition of missing pinmux and uart nodes for AM64, AM62x, AM62A,
   J721e, J7200 that are used by bootloader
 - Split Pinmux regions/range to avoid holes for J721s2, J7200, J784s4
 - Drop bootargs and unneeded aliases across all K3 SoCs
 - Move aliases to board dts files from SoC dtsi files
 - Move to generic node name for can, rtc nodes on am65
 - s/-pins-default/default-pins/ to match upcoming pinctrl.yaml update
 - Fix pinctrl phandle references to use <> as separator where multiple
   entries are present

* tag 'ti-k3-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (153 commits)
  arm64: dts: ti: Unify pin group node names for make dtbs checks
  arm64: dts: ti: add verdin am62 yavia
  arm64: dts: ti: add verdin am62 dahlia
  arm64: dts: ti: add verdin am62
  dt-bindings: arm: ti: add toradex,verdin-am62 et al.
  arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625
  dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware
  arm64: dts: ti: k3-j7200-mcu-wakeup: Remove 0x unit address prefix from nodename
  arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom
  arm64: dts: ti: k3-am64: Add ESM support
  arm64: dts: ti: k3-am62: Add ESM support
  arm64: dts: ti: k3-j7200: Add ESM support
  arm64: dts: ti: k3-j721e: Add ESM support
  dt-bindings: misc: esm: Add ESM support for TI K3 devices
  arm64: dts: ti: k3-j721s2-som-p0: Enable wakeup_i2c0 and eeprom
  arm64: dts: ti: k3-j721s2-common-proc-board: Add uart pinmux
  arm64: dts: ti: k3-am68-sk-som: Enable wakeup_i2c0 and eeprom
  arm64: dts: ti: k3-am68-sk-base-board: Add uart pinmux
  arm64: dts: ti: k3-am68-sk-base-board: Add pinmux for RPi Header
  arm64: dts: ti: k3-j721s2: Fix wkup pinmux range
  ...

Link: https://lore.kernel.org/r/7fe0c6de-cb99-9c89-8583-b3855fde16f8@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-06-20 22:51:55 +02:00
commit af3c684721
80 changed files with 8770 additions and 864 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
Documentation/devicetree/bindings/arm/ti/k3.yaml
View File

@ -25,6 +25,12 @@ properties:
- ti,am62a7-sk
- const: ti,am62a7
- description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
items:
- const: phytec,am625-phyboard-lyra-rdk
- const: phytec,am62-phycore-som
- const: ti,am625
- description: K3 AM625 SoC
items:
- enum:
@ -33,6 +39,26 @@ properties:
- ti,am62-lp-sk
- const: ti,am625
- description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards
items:
- enum:
- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
- const: toradex,verdin-am62 # Verdin AM62 Module
- const: ti,am625
- description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT
items:
- enum:
- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
- const: toradex,verdin-am62 # Verdin AM62 Module
- const: ti,am625
- description: K3 AM642 SoC
items:
- enum:

53
Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml Normal file
View File

@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Texas Instruments Incorporated
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments K3 ESM
maintainers:
- Neha Malcom Francis <n-francis@ti.com>
description:
The ESM (Error Signaling Module) is an IP block on TI K3 devices
that allows handling of safety events somewhat similar to what interrupt
controller would do. The safety signals have their separate paths within
the SoC, and they are handled by the ESM, which routes them to the proper
destination, which can be system reset, interrupt controller, etc. In the
simplest configuration the signals are just routed to reset the SoC.
properties:
compatible:
const: ti,j721e-esm
reg:
maxItems: 1
ti,esm-pins:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
integer array of ESM interrupt pins to route to external event pin
which can be used to reset the SoC.
minItems: 1
maxItems: 255
required:
- compatible
- reg
- ti,esm-pins
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <344>, <345>;
};
};

9
arch/arm64/boot/dts/ti/Makefile
View File

@ -10,7 +10,14 @@
# Boards with AM62x SoC
dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
# Boards with AM62Ax SoC
@ -22,12 +29,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
# Boards with AM65x SoC
k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
# Boards with J7200 SoC
k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo

6
arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts
View File

@ -73,19 +73,19 @@
};
&main_pmx0 {
vddshv_sdio_pins_default: vddshv-sdio-pins-default {
vddshv_sdio_pins_default: vddshv-sdio-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */
>;
};
pmic_irq_pins_default: pmic-irq-pins-default {
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (B16) EXTINTn */
>;

21
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
View File

@ -184,6 +184,21 @@
dma-names = "tx", "rx1", "rx2";
};
secure_proxy_sa3: mailbox@43600000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x43600000 0x00 0x10000>,
<0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
@ -192,6 +207,12 @@
pinctrl-single,function-mask = <0xffffffff>;
};
main_esm: esm@420000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;

6
arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi
View File

@ -14,6 +14,12 @@
pinctrl-single,function-mask = <0xffffffff>;
};
mcu_esm: esm@4100000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;
};
/*
* The MCU domain timer interrupts are routed only to the ESM module,
* and not currently available for Linux. The MCU domain timers are

324
arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi Normal file
View File

@ -0,0 +1,324 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
* https://www.phytec.com/product/phycore-am62x
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "PHYTEC phyCORE-AM62x";
compatible = "phytec,am62-phycore-som", "ti,am625";
aliases {
ethernet0 = &cpsw_port1;
gpio0 = &main_gpio0;
gpio1 = &main_gpio1;
i2c0 = &main_i2c0;
mmc0 = &sdhci0;
rtc0 = &i2c_som_rtc;
rtc1 = &wkup_rtc0;
spi0 = &ospi0;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ramoops@9ca00000 {
compatible = "ramoops";
reg = <0x00 0x9ca00000 0x00 0x00100000>;
record-size = <0x8000>;
console-size = <0x8000>;
ftrace-size = <0x00>;
pmsg-size = <0x8000>;
};
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
alignment = <0x1000>;
no-map;
};
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9db00000 0x00 0x00c00000>;
no-map;
};
};
vcc_5v0_som: regulator-vcc-5v0-som {
compatible = "regulator-fixed";
regulator-name = "VCC_5V0_SOM";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_1v8: regulator-vdd-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_5v0_som>;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
};
};
};
&main_pmx0 {
leds_pins_default: leds-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
main_mdio1_pins_default: main-mdio1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
>;
};
main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */
AM62X_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA2) MMC0_DAT0 */
AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */
AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */
AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */
AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */
AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */
AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */
AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */
>;
};
main_rgmii1_pins_default: main-rgmii1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
>;
};
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
>;
};
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */
>;
};
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
status = "okay";
cpsw3g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
status = "okay";
pmic@30 {
compatible = "ti,tps65219";
reg = <0x30>;
buck1-supply = <&vcc_5v0_som>;
buck2-supply = <&vcc_5v0_som>;
buck3-supply = <&vcc_5v0_som>;
ldo1-supply = <&vdd_3v3>;
ldo2-supply = <&vdd_1v8>;
ldo3-supply = <&vcc_5v0_som>;
ldo4-supply = <&vcc_5v0_som>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
ti,power-button;
system-power-controller;
regulators {
vdd_core: buck1 {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-boot-on;
regulator-always-on;
};
vdd_3v3: buck2 {
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ddr4: buck3 {
regulator-name = "VDD_DDR4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
vddshv5_sdio: ldo1 {
regulator-name = "VDDSHV5_SDIO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-allow-bypass;
regulator-boot-on;
regulator-always-on;
};
vddr_core: ldo2 {
regulator-name = "VDDR_CORE";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
vdda_1v8: ldo3 {
regulator-name = "VDDA_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vdd_2v5: ldo4 {
regulator-name = "VDD_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-boot-on;
regulator-always-on;
};
};
};
eeprom@50 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x50>;
};
i2c_som_rtc: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
status = "okay";
serial_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
};
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
non-removable;
status = "okay";
};

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@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
thermal_zones: thermal-zones {
main0_thermal: main0-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 0>;
trips {
main0_crit: main0-crit {
temperature = <105000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main1_thermal: main1-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 1>;
trips {
main1_crit: main1-crit {
temperature = <105000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
};

161
arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi Normal file
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@ -0,0 +1,161 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* Common dtsi for Verdin AM62 SoM on Dahlia carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
*/
/* Verdin ETHs */
&cpsw3g {
status = "okay";
};
/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
status = "okay";
};
/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
status = "okay";
};
/* Verdin PWM_1, PWM_2 */
&epwm0 {
status = "okay";
};
/* Verdin PWM_3_DSI */
&epwm1 {
status = "okay";
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>,
<&pinctrl_gpio_5>,
<&pinctrl_gpio_6>,
<&pinctrl_gpio_7>,
<&pinctrl_gpio_8>;
};
/* Verdin I2C_1 */
&main_i2c1 {
status = "okay";
/* Current measurement into module VCC */
hwmon@40 {
compatible = "ti,ina219";
reg = <0x40>;
shunt-resistor = <10000>;
};
/* Temperature sensor */
sensor@4f {
compatible = "ti,tmp75c";
reg = <0x4f>;
};
/* EEPROM */
eeprom@57 {
compatible = "st,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* Verdin I2C_2_DSI */
&main_i2c2 {
status = "okay";
};
/* Verdin I2C_4_CSI */
&main_i2c3 {
status = "okay";
};
/* Verdin CAN_1 */
&main_mcan0 {
status = "okay";
};
/* Verdin SPI_1 */
&main_spi1 {
status = "okay";
};
/* Verdin UART_3 */
&main_uart0 {
status = "okay";
};
/* Verdin UART_1 */
&main_uart1 {
status = "okay";
};
/* Verdin I2S_1 */
&mcasp0 {
status = "okay";
};
&mcu_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_1>,
<&pinctrl_gpio_2>,
<&pinctrl_gpio_3>,
<&pinctrl_gpio_4>;
};
/* Verdin I2C_3_HDMI */
&mcu_i2c0 {
status = "okay";
};
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
};
/* Verdin QSPI_1 */
&ospi0 {
status = "okay";
};
/* Verdin SD_1 */
&sdhci1 {
ti,driver-strength-ohm = <33>;
status = "okay";
};
/* Verdin USB_1 */
&usbss0 {
status = "okay";
};
&usb0 {
status = "okay";
};
/* Verdin USB_2 */
&usbss1 {
status = "okay";
};
&usb1 {
status = "okay";
};
/* Verdin CTRL_WAKE1_MICO# */
&verdin_gpio_keys {
status = "okay";
};
/* Verdin UART_2 */
&wkup_uart0 {
/* FIXME: WKUP UART0 is used by DM firmware */
status = "reserved";
};

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arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi Normal file
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@ -0,0 +1,190 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* Common dtsi for Verdin AM62 SoM on Development carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
/* Verdin ETHs */
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>;
status = "okay";
};
/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
status = "okay";
cpsw3g_phy1: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
interrupt-parent = <&main_gpio0>;
interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
micrel,led-mode = <0>;
};
};
/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
status = "okay";
};
/* Verdin ETH_2_RGMII */
&cpsw_port2 {
phy-handle = <&cpsw3g_phy1>;
phy-mode = "rgmii-rxid";
status = "okay";
};
/* Verdin PWM_1, PWM_2 */
&epwm0 {
status = "okay";
};
/* Verdin PWM_3_DSI */
&epwm1 {
status = "okay";
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>,
<&pinctrl_gpio_5>,
<&pinctrl_gpio_6>,
<&pinctrl_gpio_7>,
<&pinctrl_gpio_8>;
};
/* Verdin I2C_1 */
&main_i2c1 {
status = "okay";
/* IO Expander */
gpio_expander_21: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
};
/* Current measurement into module VCC */
hwmon@40 {
compatible = "ti,ina219";
reg = <0x40>;
shunt-resistor = <10000>;
};
/* Temperature sensor */
sensor@4f {
compatible = "ti,tmp75c";
reg = <0x4f>;
};
/* EEPROM */
eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* Verdin I2C_2_DSI */
&main_i2c2 {
status = "okay";
};
/* Verdin I2C_4_CSI */
&main_i2c3 {
status = "okay";
};
/* Verdin CAN_1 */
&main_mcan0 {
status = "okay";
};
/* Verdin SPI_1 */
&main_spi1 {
status = "okay";
};
/* Verdin UART_3 */
&main_uart0 {
status = "okay";
};
/* Verdin UART_1, connector X50 through RS485 transceiver. */
&main_uart1 {
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
status = "okay";
};
/* Verdin I2S_1 */
&mcasp0 {
status = "okay";
};
&mcu_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_1>,
<&pinctrl_gpio_2>,
<&pinctrl_gpio_3>,
<&pinctrl_gpio_4>;
};
/* Verdin I2C_3_HDMI */
&mcu_i2c0 {
status = "okay";
};
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
};
/* Verdin QSPI_1 */
&ospi0 {
status = "okay";
};
/* Verdin SD_1 */
&sdhci1 {
ti,driver-strength-ohm = <33>;
status = "okay";
};
/* Verdin USB_1 */
&usbss0 {
status = "okay";
};
&usb0 {
status = "okay";
};
/* Verdin USB_2 */
&usbss1 {
status = "okay";
};
&usb1 {
status = "okay";
};
/* Verdin CTRL_WAKE1_MICO# */
&verdin_gpio_keys {
status = "okay";
};
/* Verdin UART_2 */
&wkup_uart0 {
/* FIXME: WKUP UART0 is used by DM firmware */
status = "reserved";
};

20
arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi Normal file
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@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* Common dtsi for Verdin AM62 SoM non-WB variant
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
*/
&sdhci2 {
pinctrl-0 = <&pinctrl_sdhci2>;
bus-width = <4>;
status = "disabled";
};
&main_uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "disabled";
};

39
arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi Normal file
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@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* Common dtsi for Verdin AM62 SoM WB variant
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
*/
/ {
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_en>;
reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>;
};
};
/* On-module Wi-Fi */
&sdhci2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci2>;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
ti,fails-without-test-cd;
ti,driver-strength-ohm = <50>;
vmmc-supply = <&reg_3v3>;
status = "okay";
};
/* On-module Bluetooth */
&main_uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};

207
arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi Normal file
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@ -0,0 +1,207 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* Common dtsi for Verdin AM62 SoM on Yavia carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/yavia
*/
#include <dt-bindings/leds/common.h>
/ {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_clk_gpio>,
<&pinctrl_qspi1_cs_gpio>,
<&pinctrl_qspi1_io0_gpio>,
<&pinctrl_qspi1_io1_gpio>,
<&pinctrl_qspi1_io2_gpio>,
<&pinctrl_qspi1_io3_gpio>;
/* SODIMM 52 - LD1_RED */
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 54 - LD1_GREEN */
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 56 - LD1_BLUE */
led-2 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 58 - LD2_RED */
led-3 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 60 - LD2_GREEN */
led-4 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 62 - LD2_BLUE */
led-5 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
};
};
};
/* Verdin ETHs */
&cpsw3g {
status = "okay";
};
/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */
&cpsw3g_mdio {
status = "okay";
};
/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
status = "okay";
};
/* Verdin PWM_1, PWM_2 */
&epwm0 {
status = "okay";
};
/* Verdin PWM_3_DSI */
&epwm1 {
status = "okay";
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>,
<&pinctrl_gpio_5>,
<&pinctrl_gpio_6>,
<&pinctrl_gpio_7>,
<&pinctrl_gpio_8>,
<&pinctrl_qspi1_cs2_gpio>;
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>;
};
/* Verdin I2C_1 */
&main_i2c1 {
status = "okay";
/* Temperature sensor */
sensor@4f {
compatible = "ti,tmp75c";
reg = <0x4f>;
};
/* EEPROM */
eeprom@57 {
compatible = "st,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* Verdin I2C_2_DSI */
&main_i2c2 {
status = "okay";
};
/* Verdin I2C_4_CSI */
&main_i2c3 {
status = "okay";
};
/* Verdin CAN_1 */
&main_mcan0 {
status = "okay";
};
/* Verdin SPI_1 */
&main_spi1 {
status = "okay";
};
/* Verdin UART_3 */
&main_uart0 {
status = "okay";
};
/* Verdin UART_1 */
&main_uart1 {
status = "okay";
};
&mcu_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_1>,
<&pinctrl_gpio_2>,
<&pinctrl_gpio_3>,
<&pinctrl_gpio_4>;
};
/* Verdin I2C_3_HDMI */
&mcu_i2c0 {
status = "okay";
};
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
};
/* Verdin SD_1 */
&sdhci1 {
status = "okay";
};
/* Verdin USB_1 */
&usbss0 {
status = "okay";
};
&usb0 {
status = "okay";
};
/* Verdin USB_2 */
&usbss1 {
status = "okay";
};
&usb1 {
status = "okay";
};
/* Verdin CTRL_WAKE1_MICO# */
&verdin_gpio_keys {
status = "okay";
};
/* Verdin UART_2 */
&wkup_uart0 {
/* FIXME: WKUP UART0 is used by DM firmware */
status = "reserved";
};

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arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi Normal file
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File diff suppressed because it is too large Load Diff

8
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
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@ -61,4 +61,12 @@
/* Used by DM firmware */
status = "reserved";
};
wkup_vtm0: temperature-sensor@b00000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0xb00000 0x00 0x400>,
<0x00 0xb01000 0x00 0x400>;
power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
};

8
arch/arm64/boot/dts/ti/k3-am62.dtsi
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@ -81,6 +81,7 @@
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
/* Wakeup Domain Range */
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
@ -91,14 +92,17 @@
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
cbass_wakeup: bus@2b000000 {
cbass_wakeup: bus@b00000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
};
};
#include "k3-am62-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */

52
arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
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@ -216,7 +216,7 @@
};
&main_pmx0 {
gpio0_pins_default: gpio0-pins-default {
gpio0_pins_default: gpio0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
@ -235,47 +235,47 @@
>;
};
vdd_sd_dv_pins_default: vdd-sd-pins-default {
vdd_sd_dv_pins_default: vdd-sd-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
>;
};
usr_button_pins_default: usr-button-pins-default {
usr_button_pins_default: usr-button-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */
>;
};
grove_pins_default: grove-pins-default {
grove_pins_default: grove-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
local_i2c_pins_default: local-i2c-pins-default {
local_i2c_pins_default: local-i2c-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
i2c2_1v8_pins_default: i2c2-pins-default {
i2c2_1v8_pins_default: i2c2-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
mdio0_pins_default: mdio0-pins-default {
mdio0_pins_default: mdio0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */
AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */
>;
};
rgmii1_pins_default: rgmii1-pins-default {
rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
@ -292,7 +292,7 @@
>;
};
emmc_pins_default: emmc-pins-default {
emmc_pins_default: emmc-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
@ -307,13 +307,13 @@
>;
};
vdd_3v3_sd_pins_default: vdd-3v3-sd-pins-default {
vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
>;
};
sd_pins_default: sd-pins-default {
sd_pins_default: sd-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@ -325,7 +325,7 @@
>;
};
wifi_pins_default: wifi-pins-default {
wifi_pins_default: wifi-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */
AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */
@ -338,19 +338,19 @@
>;
};
wifi_en_pins_default: wifi-en-pins-default {
wifi_en_pins_default: wifi-en-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */
>;
};
wifi_wlirq_pins_default: wifi-wlirq-pins-default {
wifi_wlirq_pins_default: wifi-wlirq-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */
>;
};
spe_pins_default: spe-pins-default {
spe_pins_default: spe-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */
AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */
@ -366,21 +366,21 @@
>;
};
mikrobus_i2c_pins_default: mikrobus-i2c-pins-default {
mikrobus_i2c_pins_default: mikrobus-i2c-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */
AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */
>;
};
mikrobus_uart_pins_default: mikrobus-uart-pins-default {
mikrobus_uart_pins_default: mikrobus-uart-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */
AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */
>;
};
mikrobus_spi_pins_default: mikrobus-spi-pins-default {
mikrobus_spi_pins_default: mikrobus-spi-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
@ -389,7 +389,7 @@
>;
};
mikrobus_gpio_pins_default: mikrobus-gpio-pins-default {
mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
@ -397,27 +397,27 @@
>;
};
console_pins_default: console-pins-default {
console_pins_default: console-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
>;
};
wifi_debug_uart_pins_default: wifi-debug-uart-pins-default {
wifi_debug_uart_pins_default: wifi-debug-uart-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */
AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */
>;
};
usb1_pins_default: usb1-pins-default {
usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */
>;
};
pmic_irq_pins_default: pmic-irq-pins-default {
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */
>;
@ -425,7 +425,7 @@
};
&mcu_pmx0 {
i2c_qwiic_pins_default: i2c-qwiic-pins-default {
i2c_qwiic_pins_default: i2c-qwiic-default-pins {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */
AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */
@ -438,14 +438,14 @@
>;
};
i2c_csi_pins_default: i2c-csi-pins-default {
i2c_csi_pins_default: i2c-csi-default-pins {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */
AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */
>;
};
wifi_32k_clk: mcu-clk-out-pins-default {
wifi_32k_clk: mcu-clk-out-default-pins {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */
>;

266
arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts Normal file
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@ -0,0 +1,266 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH
* Author: Wadim Egorov <w.egorov@phytec.de>
*
* Product homepage:
* https://www.phytec.com/product/phyboard-am62x
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am625.dtsi"
#include "k3-am62-phycore-som.dtsi"
/ {
compatible = "phytec,am625-phyboard-lyra-rdk",
"phytec,am62-phycore-som", "ti,am625";
model = "PHYTEC phyBOARD-Lyra AM625";
aliases {
serial2 = &main_uart0;
serial3 = &main_uart1;
mmc1 = &sdhci1;
usb0 = &usb0;
usb1 = &usb1;
ethernet1 = &cpsw_port2;
};
can_tc1: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
};
keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins_default>;
key-home {
label = "home";
linux,code = <KEY_HOME>;
gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>;
};
key-menu {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
led-1 {
gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
led-2 {
gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
};
};
vcc_3v3_mmc: regulator-vcc-3v3-mmc {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3_MMC";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
&main_pmx0 {
gpio_keys_pins_default: gpio-keys-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
>;
};
gpio_exp_int_pins_default: gpio-exp-int-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */
AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */
>;
};
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */
AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */
AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */
AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */
AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */
AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */
AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */
>;
};
main_rgmii2_pins_default: main-rgmii2-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
>;
};
main_usb1_pins_default: main-usb1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
>;
};
user_leds_pins_default: user-leds-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */
>;
};
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
};
&cpsw3g_mdio {
cpsw3g_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
status = "okay";
gpio_exp: gpio-expander@21 {
pinctrl-names = "default";
pinctrl-0 = <&gpio_exp_int_pins_default>;
compatible = "nxp,pcf8574";
reg = <0x21>;
interrupt-parent = <&main_gpio1>;
interrupts = <49 0>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
gpio-line-names = "GPIO0_HDMI_RST", "GPIO1_CAN0_nEN",
"GPIO2_LED2", "GPIO3_LVDS_GPIO",
"GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN",
"GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET";
};
eeprom@51 {
compatible = "atmel,24c02";
pagesize = <16>;
reg = <0x51>;
};
};
&main_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&can_tc1>;
status = "okay";
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
};
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
/* Main UART1 may be used by TIFS firmware */
status = "okay";
};
&sdhci1 {
vmmc-supply = <&vcc_3v3_mmc>;
vqmmc-supply = <&vddshv5_sdio>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
no-1-8-v;
status = "okay";
};
&usbss0 {
ti,vbus-divider;
status = "okay";
};
&usbss1 {
ti,vbus-divider;
status = "okay";
};
&usb0 {
dr_mode = "peripheral";
};
&usb1 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&main_usb1_pins_default>;
};

13
arch/arm64/boot/dts/ti/k3-am625-sk.dts
View File

@ -101,7 +101,7 @@
};
&main_pmx0 {
main_rgmii2_pins_default: main-rgmii2-pins-default {
main_rgmii2_pins_default: main-rgmii2-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
@ -118,7 +118,7 @@
>;
};
ospi0_pins_default: ospi0-pins-default {
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
@ -134,13 +134,13 @@
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
>;
@ -161,7 +161,7 @@
"UART1_FET_BUF_EN", "WL_LT_EN",
"GPIO_HDMI_RSTn", "CSI_GPIO1",
"CSI_GPIO2", "PRU_3V3_EN",
"HDMI_INTn", "TEST_GPIO2",
"HDMI_INTn", "PD_I2C_IRQ",
"MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
"MCASP1_FET_SEL", "UART1_FET_SEL",
"TSINT#", "IO_EXP_TEST_LED";
@ -183,8 +183,7 @@
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default
&main_rgmii2_pins_default>;
pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
};
&cpsw_port2 {

22
arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
*/
/dts-v1/;
#include "k3-am625.dtsi"
#include "k3-am62-verdin.dtsi"
#include "k3-am62-verdin-nonwifi.dtsi"
#include "k3-am62-verdin-dahlia.dtsi"
/ {
model = "Toradex Verdin AM62 on Dahlia Board";
compatible = "toradex,verdin-am62-nonwifi-dahlia",
"toradex,verdin-am62-nonwifi",
"toradex,verdin-am62",
"ti,am625";
};

22
arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
/dts-v1/;
#include "k3-am625.dtsi"
#include "k3-am62-verdin.dtsi"
#include "k3-am62-verdin-nonwifi.dtsi"
#include "k3-am62-verdin-dev.dtsi"
/ {
model = "Toradex Verdin AM62 on Verdin Development Board";
compatible = "toradex,verdin-am62-nonwifi-dev",
"toradex,verdin-am62-nonwifi",
"toradex,verdin-am62",
"ti,am625";
};

22
arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/yavia
*/
/dts-v1/;
#include "k3-am625.dtsi"
#include "k3-am62-verdin.dtsi"
#include "k3-am62-verdin-nonwifi.dtsi"
#include "k3-am62-verdin-yavia.dtsi"
/ {
model = "Toradex Verdin AM62 on Yavia Board";
compatible = "toradex,verdin-am62-nonwifi-yavia",
"toradex,verdin-am62-nonwifi",
"toradex,verdin-am62",
"ti,am625";
};

22
arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
*/
/dts-v1/;
#include "k3-am625.dtsi"
#include "k3-am62-verdin.dtsi"
#include "k3-am62-verdin-wifi.dtsi"
#include "k3-am62-verdin-dahlia.dtsi"
/ {
model = "Toradex Verdin AM62 WB on Dahlia Board";
compatible = "toradex,verdin-am62-wifi-dahlia",
"toradex,verdin-am62-wifi",
"toradex,verdin-am62",
"ti,am625";
};

22
arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/verdin-development-board-kit
*/
/dts-v1/;
#include "k3-am625.dtsi"
#include "k3-am62-verdin.dtsi"
#include "k3-am62-verdin-wifi.dtsi"
#include "k3-am62-verdin-dev.dtsi"
/ {
model = "Toradex Verdin AM62 WB on Verdin Development Board";
compatible = "toradex,verdin-am62-wifi-dev",
"toradex,verdin-am62-wifi",
"toradex,verdin-am62",
"ti,am625";
};

22
arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/yavia
*/
/dts-v1/;
#include "k3-am625.dtsi"
#include "k3-am62-verdin.dtsi"
#include "k3-am62-verdin-wifi.dtsi"
#include "k3-am62-verdin-yavia.dtsi"
/ {
model = "Toradex Verdin AM62 WB on Yavia Board";
compatible = "toradex,verdin-am62-wifi-yavia",
"toradex,verdin-am62-wifi",
"toradex,verdin-am62",
"ti,am625";
};

156
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
View File

@ -169,6 +169,21 @@
};
};
secure_proxy_sa3: mailbox@43600000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x43600000 0x00 0x10000>,
<0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
@ -177,6 +192,102 @@
pinctrl-single,function-mask = <0xffffffff>;
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 36 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 36 2>;
assigned-clock-parents = <&k3_clks 36 3>;
power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 37 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 37 2>;
assigned-clock-parents = <&k3_clks 37 3>;
power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 38 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 38 2>;
assigned-clock-parents = <&k3_clks 38 3>;
power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 39 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 39 2>;
assigned-clock-parents = <&k3_clks 39 3>;
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 40 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 40 2>;
assigned-clock-parents = <&k3_clks 40 3>;
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 41 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 41 2>;
assigned-clock-parents = <&k3_clks 41 3>;
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 42 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 42 2>;
assigned-clock-parents = <&k3_clks 42 3>;
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 43 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 43 2>;
assigned-clock-parents = <&k3_clks 43 3>;
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@ -601,6 +712,51 @@
status = "disabled";
};
main_rti0: watchdog@e000000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e000000 0x00 0x100>;
clocks = <&k3_clks 125 0>;
power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 125 0>;
assigned-clock-parents = <&k3_clks 125 2>;
};
main_rti1: watchdog@e010000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e010000 0x00 0x100>;
clocks = <&k3_clks 126 0>;
power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 126 0>;
assigned-clock-parents = <&k3_clks 126 2>;
};
main_rti2: watchdog@e020000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e020000 0x00 0x100>;
clocks = <&k3_clks 127 0>;
power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 127 0>;
assigned-clock-parents = <&k3_clks 127 2>;
};
main_rti3: watchdog@e030000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e030000 0x00 0x100>;
clocks = <&k3_clks 128 0>;
power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 128 0>;
assigned-clock-parents = <&k3_clks 128 2>;
};
main_rti4: watchdog@e040000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x0e040000 0x00 0x100>;
clocks = <&k3_clks 205 0>;
power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 205 0>;
assigned-clock-parents = <&k3_clks 205 2>;
};
epwm0: pwm@23000000 {
compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;

56
arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi
View File

@ -15,6 +15,51 @@
status = "disabled";
};
/*
* The MCU domain timer interrupts are routed only to the ESM module,
* and not currently available for Linux. The MCU domain timers are
* of limited use without interrupts, and likely reserved by the ESM.
*/
mcu_timer0: timer@4800000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4800000 0x00 0x400>;
clocks = <&k3_clks 35 2>;
clock-names = "fck";
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer1: timer@4810000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4810000 0x00 0x400>;
clocks = <&k3_clks 48 2>;
clock-names = "fck";
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer2: timer@4820000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4820000 0x00 0x400>;
clocks = <&k3_clks 49 2>;
clock-names = "fck";
power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer3: timer@4830000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4830000 0x00 0x400>;
clocks = <&k3_clks 50 2>;
clock-names = "fck";
power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
@ -87,4 +132,15 @@
clock-names = "gpio";
status = "disabled";
};
mcu_rti0: watchdog@4880000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x04880000 0x00 0x100>;
clocks = <&k3_clks 131 0>;
power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 131 0>;
assigned-clock-parents = <&k3_clks 131 2>;
/* Tightly coupled to M4F */
status = "reserved";
};
};

47
arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi Normal file
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@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
thermal_zones: thermal-zones {
main0_thermal: main0-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 0>;
trips {
main0_crit: main0-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main1_thermal: main1-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 1>;
trips {
main1_crit: main1-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main2_thermal: main2-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&wkup_vtm0 2>;
trips {
main2_crit: main2-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
};

19
arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi
View File

@ -51,4 +51,23 @@
wakeup-source;
status = "disabled";
};
wkup_rti0: watchdog@2b000000 {
compatible = "ti,j7-rti-wdt";
reg = <0x00 0x2b000000 0x00 0x100>;
clocks = <&k3_clks 132 0>;
power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 132 0>;
assigned-clock-parents = <&k3_clks 132 2>;
/* Used by DM firmware */
status = "reserved";
};
wkup_vtm0: temperature-sensor@b00000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0xb00000 0x00 0x400>,
<0x00 0xb01000 0x00 0x400>;
power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
};

2
arch/arm64/boot/dts/ti/k3-am62a.dtsi
View File

@ -115,6 +115,8 @@
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
};
};
#include "k3-am62a-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */

60
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
View File

@ -17,7 +17,9 @@
model = "Texas Instruments AM62A7 SK";
aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
mmc1 = &sdhci1;
};
@ -114,36 +116,63 @@
};
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
>;
};
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "reserved";
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@ -155,26 +184,26 @@
>;
};
usr_led_pins_default: usr-led-pins-default {
usr_led_pins_default: usr-led-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
>;
};
main_usb1_pins_default: main-usb1-pins-default {
main_usb1_pins_default: main-usb1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
>;
};
main_mdio1_pins_default: main-mdio1-pins-default {
main_mdio1_pins_default: main-mdio1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
>;
};
main_rgmii1_pins_default: main-rgmii1-pins-default {
main_rgmii1_pins_default: main-rgmii1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
@ -254,6 +283,13 @@
pinctrl-0 = <&main_uart0_pins_default>;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "reserved";
};
&usbss1 {
status = "okay";
};

97
arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
View File

@ -25,14 +25,12 @@
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
@ -120,35 +118,44 @@
&main_pmx0 {
/* First pad number is ALW package and second is AMC package */
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */
AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */
AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */
AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */
>;
};
main_mmc0_pins_default: main-mmc0-pins-default {
main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */
@ -163,7 +170,7 @@
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */
AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */
@ -175,20 +182,20 @@
>;
};
usr_led_pins_default: usr-led-pins-default {
usr_led_pins_default: usr-led-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */
>;
};
main_mdio1_pins_default: main-mdio1-pins-default {
main_mdio1_pins_default: main-mdio1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */
AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */
>;
};
main_rgmii1_pins_default: main-rgmii1-pins-default {
main_rgmii1_pins_default: main-rgmii1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */
@ -205,18 +212,29 @@
>;
};
main_usb1_pins_default: main-usb1-pins-default {
main_usb1_pins_default: main-usb1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */
>;
};
main_mcasp1_pins_default: main-mcasp1-pins-default {
main_mcasp1_pins_default: main-mcasp1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */
AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */
AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */
AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */
AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */
AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */
AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */
AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
>;
};
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */
>;
};
};
@ -224,6 +242,8 @@
&wkup_uart0 {
/* WKUP UART0 is used by DM firmware */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&main_uart0 {
@ -235,6 +255,8 @@
&main_uart1 {
/* Main UART1 is used by TIFS firmware */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_i2c0 {
@ -242,6 +264,36 @@
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@51 {
/* AT24C512C-MAHM-T or M24512-DFMC6TG */
compatible = "atmel,24c512";
reg = <0x51>;
};
typec_pd0: tps6598x@3f {
compatible = "ti,tps6598x";
reg = <0x3f>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
self-powered;
data-role = "dual";
power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_con_hs: endpoint {
remote-endpoint = <&usb0_hs_ep>;
};
};
};
};
};
};
&main_i2c1 {
@ -321,7 +373,16 @@
};
&usb0 {
dr_mode = "peripheral";
#address-cells = <1>;
#size-cells = <0>;
usb-role-switch;
port@0 {
reg = <0>;
usb0_hs_ep: endpoint {
remote-endpoint = <&usb_con_hs>;
};
};
};
&usb1 {

171
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
View File

@ -228,12 +228,161 @@
};
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 36 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 36 1>;
assigned-clock-parents = <&k3_clks 36 2>;
power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 37 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 37 1>;
assigned-clock-parents = <&k3_clks 37 2>;
power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 38 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 38 1>;
assigned-clock-parents = <&k3_clks 38 2>;
power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 39 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 39 1>;
assigned-clock-parents = <&k3_clks 39 2>;
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 40 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 40 1>;
assigned-clock-parents = <&k3_clks 40 2>;
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 41 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 41 1>;
assigned-clock-parents = <&k3_clks 41 2>;
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 42 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 42 1>;
assigned-clock-parents = <&k3_clks 42 2>;
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 43 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 43 1>;
assigned-clock-parents = <&k3_clks 43 2>;
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer8: timer@2480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2480000 0x00 0x400>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 44 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 44 1>;
assigned-clock-parents = <&k3_clks 44 2>;
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer9: timer@2490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2490000 0x00 0x400>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 45 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 45 1>;
assigned-clock-parents = <&k3_clks 45 2>;
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer10: timer@24a0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24a0000 0x00 0x400>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 46 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 46 1>;
assigned-clock-parents = <&k3_clks 46 2>;
power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer11: timer@24b0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24b0000 0x00 0x400>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 47 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 47 1>;
assigned-clock-parents = <&k3_clks 47 2>;
power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_esm: esm@420000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>;
};
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
@ -245,7 +394,6 @@
reg = <0x00 0x02810000 0x00 0x100>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
@ -257,7 +405,6 @@
reg = <0x00 0x02820000 0x00 0x100>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 0>;
clock-names = "fclk";
@ -269,7 +416,6 @@
reg = <0x00 0x02830000 0x00 0x100>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 154 0>;
clock-names = "fclk";
@ -281,7 +427,6 @@
reg = <0x00 0x02840000 0x00 0x100>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 155 0>;
clock-names = "fclk";
@ -293,7 +438,6 @@
reg = <0x00 0x02850000 0x00 0x100>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 156 0>;
clock-names = "fclk";
@ -305,7 +449,6 @@
reg = <0x00 0x02860000 0x00 0x100>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 158 0>;
clock-names = "fclk";
@ -676,6 +819,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
mailbox0_cluster3: mailbox@29030000 {
@ -686,6 +830,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
mailbox0_cluster4: mailbox@29040000 {
@ -696,6 +841,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
mailbox0_cluster5: mailbox@29050000 {
@ -706,6 +852,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
mailbox0_cluster6: mailbox@29060000 {
@ -715,6 +862,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
mailbox0_cluster7: mailbox@29070000 {
@ -724,6 +872,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
status = "disabled";
};
main_r5fss0: r5fss@78000000 {
@ -1392,4 +1541,12 @@
clock-names = "fck";
status = "disabled";
};
main_vtm0: temperature-sensor@b00000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0xb00000 0x00 0x400>,
<0x00 0xb01000 0x00 0x400>;
power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
};

53
arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
View File

@ -6,11 +6,55 @@
*/
&cbass_mcu {
/*
* The MCU domain timer interrupts are routed only to the ESM module,
* and not currently available for Linux. The MCU domain timers are
* of limited use without interrupts, and likely reserved by the ESM.
*/
mcu_timer0: timer@4800000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4800000 0x00 0x400>;
clocks = <&k3_clks 35 1>;
clock-names = "fck";
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer1: timer@4810000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4810000 0x00 0x400>;
clocks = <&k3_clks 48 1>;
clock-names = "fck";
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer2: timer@4820000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4820000 0x00 0x400>;
clocks = <&k3_clks 49 1>;
clock-names = "fck";
power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_timer3: timer@4830000 {
compatible = "ti,am654-timer";
reg = <0x00 0x4830000 0x00 0x400>;
clocks = <&k3_clks 50 1>;
clock-names = "fck";
power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
status = "reserved";
};
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
@ -21,7 +65,6 @@
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 160 0>;
clock-names = "fclk";
@ -109,4 +152,10 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
mcu_esm: esm@4100000 {
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>;
};
};

36
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
View File

@ -66,7 +66,7 @@
};
&main_pmx0 {
cpsw_mdio_pins_default: cpsw-mdio-pins-default {
cpsw_mdio_pins_default: cpsw-mdio-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
@ -74,7 +74,7 @@
>;
};
cpsw_rgmii1_pins_default: cpsw-rgmii1-pins-default {
cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
@ -92,26 +92,26 @@
>;
};
eeprom_wp_pins_default: eeprom-wp-pins-default {
eeprom_wp_pins_default: eeprom-wp-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */
>;
};
leds_pins_default: leds-pins-default {
leds_pins_default: leds-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
>;
};
ospi0_pins_default: ospi0-pins-default {
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
@ -160,30 +160,6 @@
status = "disabled";
};
&mailbox0_cluster2 {
status = "disabled";
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
status = "disabled";
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
status = "disabled";
};
&mailbox0_cluster7 {
status = "disabled";
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";

33
arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi Normal file
View File

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
thermal_zones: thermal-zones {
main0_thermal: main0-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&main_vtm0 0>;
trips {
main0_crit: main0-crit {
temperature = <105000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main1_thermal: main1-thermal {
polling-delay-passive = <250>; /* milliSeconds */
polling-delay = <500>; /* milliSeconds */
thermal-sensors = <&main_vtm0 1>;
trips {
main1_crit: main1-crit {
temperature = <105000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
};

19
arch/arm64/boot/dts/ti/k3-am64.dtsi
View File

@ -19,22 +19,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &mcu_uart0;
serial1 = &mcu_uart1;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
serial5 = &main_uart3;
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
chosen { };
firmware {
@ -70,6 +54,7 @@
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
@ -106,6 +91,8 @@
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
};
#include "k3-am64-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */

173
arch/arm64/boot/dts/ti/k3-am642-evm.dts
View File

@ -17,15 +17,26 @@
model = "Texas Instruments AM642 EVM";
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
stdout-path = &main_uart0;
};
aliases {
serial0 = &mcu_uart0;
serial1 = &main_uart1;
serial2 = &main_uart0;
serial3 = &main_uart3;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
@ -94,7 +105,7 @@
};
};
evm_12v0: fixedregulator-evm12v0 {
evm_12v0: regulator-0 {
/* main DC jack */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
@ -104,7 +115,7 @@
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
vsys_5v0: regulator-1 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
@ -115,7 +126,7 @@
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
vsys_3v3: regulator-2 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
@ -126,7 +137,7 @@
regulator-boot-on;
};
vdd_mmc1: fixed-regulator-sd {
vdd_mmc1: regulator-3 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@ -138,7 +149,7 @@
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
};
vddb: fixedregulator-vddb {
vddb: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
@ -148,6 +159,20 @@
regulator-boot-on;
};
vtt_supply: regulator-5 {
compatible = "regulator-fixed";
regulator-name = "vtt";
pinctrl-names = "default";
pinctrl-0 = <&ddr_vtt_pins_default>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
vin-supply = <&vsys_3v3>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
@ -201,7 +226,7 @@
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
@ -215,7 +240,16 @@
>;
};
main_uart0_pins_default: main-uart0-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
@ -224,7 +258,7 @@
>;
};
main_spi0_pins_default: main-spi0-pins-default {
main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
@ -233,21 +267,28 @@
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
mdio1_pins_default: mdio1-pins-default {
mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-pins-default {
rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
@ -264,7 +305,7 @@
>;
};
rgmii2_pins_default: rgmii2-pins-default {
rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
@ -281,13 +322,13 @@
>;
};
main_usb0_pins_default: main-usb0-pins-default {
main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
ospi0_pins_default: ospi0-pins-default {
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
@ -303,36 +344,58 @@
>;
};
main_ecap0_pins_default: main-ecap0-pins-default {
main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
main_mcan0_pins_default: main-mcan0-pins-default {
main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
>;
};
main_mcan1_pins_default: main-mcan1-pins-default {
main_mcan1_pins_default: main-mcan1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
>;
};
ddr_vtt_pins_default: ddr-vtt-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
>;
};
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
current-speed = <115200>;
};
/* main_uart1 is reserved for firmware usage */
&main_uart1 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
/* AT24CM01 */
compatible = "atmel,24c1024";
reg = <0x50>;
};
};
&main_i2c1 {
@ -425,8 +488,7 @@
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
@ -471,10 +533,53 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "ospi.tispl";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "ospi.u-boot";
reg = <0x300000 0x400000>;
};
partition@700000 {
label = "ospi.env";
reg = <0x700000 0x40000>;
};
partition@740000 {
label = "ospi.env.backup";
reg = <0x740000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@ -486,11 +591,9 @@
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@ -502,41 +605,35 @@
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&mailbox0_cluster7 {
status = "disabled";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};

51
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
View File

@ -15,6 +15,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
#include "k3-am642.dtsi"
@ -75,7 +76,7 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default &user_leds_pins_default>;
pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>;
led-1 {
color = <LED_COLOR_ID_RED>;
@ -104,47 +105,47 @@
};
&main_pmx0 {
can_tc1_pins_default: can-tc1-pins-default {
can_tc1_pins_default: can-tc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */
>;
};
can_tc2_pins_default: can-tc2-pins-default {
can_tc2_pins_default: can-tc2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */
>;
};
gpio_keys_pins_default: gpio-keys-pins-default {
gpio_keys_pins_default: gpio-keys-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */
AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */
>;
};
main_mcan0_pins_default: main-mcan0-pins-default {
main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
>;
};
main_mcan1_pins_default: main-mcan1-pins-default {
main_mcan1_pins_default: main-mcan1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
@ -157,14 +158,14 @@
>;
};
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_uart1_pins_default: main-uart1-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
@ -173,25 +174,25 @@
>;
};
main_usb0_pins_default: main-usb0-pins-default {
main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
pcie_usb_sel_pins_default: pcie-usb-sel-pins-default {
pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
>;
};
pcie0_pins_default: pcie0-pins-default {
pcie0_pins_default: pcie0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
>;
};
user_leds_pins_default: user-leds-pins-default {
user_leds_pins_default: user-leds-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */
AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */
@ -210,6 +211,26 @@
pagesize = <16>;
reg = <0x51>;
};
led-controller@62 {
compatible = "nxp,pca9533";
reg = <0x62>;
led-3 {
label = "red:user";
type = <PCA9532_TYPE_LED>;
};
led-4 {
label = "green:user";
type = <PCA9532_TYPE_LED>;
};
led-5 {
label = "blue:user";
type = <PCA9532_TYPE_LED>;
};
};
};
&main_mcan0 {
@ -230,6 +251,7 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
current-speed = <115200>;
};
&main_uart1 {
@ -237,6 +259,7 @@
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
uart-has-rtscts;
current-speed = <115200>;
};
&sdhci1 {

166
arch/arm64/boot/dts/ti/k3-am642-sk.dts
View File

@ -17,15 +17,25 @@
model = "Texas Instruments AM642 SK";
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
stdout-path = &main_uart0;
};
aliases {
serial0 = &mcu_uart0;
serial1 = &main_uart1;
serial2 = &main_uart0;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
@ -94,7 +104,7 @@
};
};
vusb_main: fixed-regulator-vusb-main5v0 {
vusb_main: regulator-0 {
/* USB MAIN INPUT 5V DC */
compatible = "regulator-fixed";
regulator-name = "vusb_main5v0";
@ -104,7 +114,7 @@
regulator-boot-on;
};
vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
vcc_3v3_sys: regulator-1 {
/* output of LP8733xx */
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
@ -115,7 +125,7 @@
regulator-boot-on;
};
vdd_mmc1: fixed-regulator-sd {
vdd_mmc1: regulator-2 {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
@ -127,7 +137,7 @@
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
com8_ls_en: regulator-1 {
com8_ls_en: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "com8_ls_en";
regulator-min-microvolt = <3300000>;
@ -139,7 +149,7 @@
gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
};
wlan_en: regulator-2 {
wlan_en: regulator-4 {
/* output of SN74AVC4T245RSVR */
compatible = "regulator-fixed";
regulator-name = "wlan_en";
@ -222,20 +232,21 @@
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
>;
};
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
@ -244,27 +255,43 @@
>;
};
main_usb0_pins_default: main-usb0-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_usb0_pins_default: main-usb0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
mdio1_pins_default: mdio1-pins-default {
mdio1_pins_default: mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-pins-default {
rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
@ -281,7 +308,7 @@
>;
};
rgmii2_pins_default: rgmii2-pins-default {
rgmii2_pins_default: rgmii2-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
@ -298,7 +325,7 @@
>;
};
ospi0_pins_default: ospi0-pins-default {
ospi0_pins_default: ospi0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
@ -314,24 +341,24 @@
>;
};
main_ecap0_pins_default: main-ecap0-pins-default {
main_ecap0_pins_default: main-ecap0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
>;
};
main_wlan_en_pins_default: main-wlan-en-pins-default {
main_wlan_en_pins_default: main-wlan-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
>;
};
main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
>;
};
main_wlan_pins_default: main-wlan-pins-default {
main_wlan_pins_default: main-wlan-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
>;
@ -342,11 +369,26 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
current-speed = <115200>;
};
&main_uart1 {
/* main_uart1 is reserved for firmware usage */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@51 {
compatible = "atmel,24c512";
reg = <0x51>;
};
};
&main_i2c1 {
@ -439,8 +481,7 @@
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
};
&cpsw_port1 {
@ -490,10 +531,53 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "ospi.tispl";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "ospi.u-boot";
reg = <0x300000 0x400000>;
};
partition@700000 {
label = "ospi.env";
reg = <0x700000 0x40000>;
};
partition@740000 {
label = "ospi.env.backup";
reg = <0x740000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@ -505,11 +589,9 @@
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
@ -521,41 +603,35 @@
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&mailbox0_cluster7 {
status = "disabled";
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};

68
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
View File

@ -21,7 +21,6 @@
chosen {
stdout-path = "serial3:115200n8";
bootargs = "earlycon=ns16550a,mmio32,0x02810000";
};
reserved-memory {
@ -105,7 +104,7 @@
};
&wkup_pmx0 {
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
/* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0)
@ -114,7 +113,7 @@
>;
};
mcu_i2c0_pins_default: mcu-i2c0-pins-default {
mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
/* (AD8) MCU_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0)
@ -123,21 +122,21 @@
>;
};
arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default {
arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins {
pinctrl-single,pins = <
/* (R2) WKUP_GPIO0_21 */
AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
>;
};
push_button_pins_default: push-button-pins-default {
push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
/* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7)
>;
};
arduino_uart_pins_default: arduino-uart-pins-default {
arduino_uart_pins_default: arduino-uart-default-pins {
pinctrl-single,pins = <
/* (P4) MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
@ -146,7 +145,7 @@
>;
};
arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default {
arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins {
pinctrl-single,pins = <
/* (P1) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
@ -155,7 +154,7 @@
>;
};
arduino_io_oe_pins_default: arduino-io-oe-pins-default {
arduino_io_oe_pins_default: arduino-io-oe-default-pins {
pinctrl-single,pins = <
/* (N4) WKUP_GPIO0_34 */
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
@ -170,7 +169,7 @@
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
/* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
@ -185,7 +184,7 @@
>;
};
db9_com_mode_pins_default: db9-com-mode-pins-default {
db9_com_mode_pins_default: db9-com-mode-default-pins {
pinctrl-single,pins = <
/* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
@ -198,7 +197,7 @@
>;
};
leds_pins_default: leds-pins-default {
leds_pins_default: leds-default-pins {
pinctrl-single,pins = <
/* (T2) WKUP_GPIO0_17, used as user led1 red */
AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
@ -211,7 +210,7 @@
>;
};
mcu_spi0_pins_default: mcu-spi0-pins-default {
mcu_spi0_pins_default: mcu-spi0-default-pins {
pinctrl-single,pins = <
/* (Y1) MCU_SPI0_CLK */
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
@ -224,7 +223,7 @@
>;
};
minipcie_pins_default: minipcie-pins-default {
minipcie_pins_default: minipcie-default-pins {
pinctrl-single,pins = <
/* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
@ -233,7 +232,7 @@
};
&main_pmx0 {
main_uart1_pins_default: main-uart1-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */
@ -242,14 +241,14 @@
>;
};
main_i2c3_pins_default: main-i2c3-pins-default {
main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
@ -262,19 +261,19 @@
>;
};
usb0_pins_default: usb0-pins-default {
usb0_pins_default: usb0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
};
usb1_pins_default: usb1-pins-default {
usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
};
arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default {
arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
@ -285,7 +284,7 @@
>;
};
dss_vout1_pins_default: dss-vout1-pins-default {
dss_vout1_pins_default: dss-vout1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */
@ -318,13 +317,13 @@
>;
};
dp_pins_default: dp-pins-default {
dp_pins_default: dp-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
@ -333,21 +332,21 @@
};
&main_pmx1 {
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
ecap0_pins_default: ecap0-pins-default {
ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
@ -385,13 +384,12 @@
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <
&arduino_io_d2_to_d3_pins_default
&arduino_i2c_aio_switch_pins_default
&arduino_io_oe_pins_default
&push_button_pins_default
&db9_com_mode_pins_default
>;
pinctrl-0 =
<&arduino_io_d2_to_d3_pins_default>,
<&arduino_i2c_aio_switch_pins_default>,
<&arduino_io_oe_pins_default>,
<&push_button_pins_default>,
<&db9_com_mode_pins_default>;
gpio-line-names =
/* 0..9 */
"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
@ -483,7 +481,7 @@
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
rtc: rtc8564@51 {
rtc: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
@ -712,11 +710,11 @@
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};

28
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
View File

@ -469,7 +469,6 @@
ti,otap-del-sel-ddr52 = <0x4>;
ti,otap-del-sel-hs200 = <0x7>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
@ -481,21 +480,6 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
pcie0_mode: pcie-mode@4060 {
compatible = "syscon";
reg = <0x00004060 0x4>;
};
pcie1_mode: pcie-mode@4070 {
compatible = "syscon";
reg = <0x00004070 0x4>;
};
pcie_devid: pcie-devid@210 {
compatible = "syscon";
reg = <0x00000210 0x4>;
};
serdes0_clk: clock@4080 {
compatible = "syscon";
reg = <0x00004080 0x4>;
@ -883,8 +867,8 @@
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
<0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
ti,syscon-pcie-id = <&pcie_devid>;
ti,syscon-pcie-mode = <&pcie0_mode>;
ti,syscon-pcie-id = <&scm_conf 0x210>;
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
@ -900,7 +884,7 @@
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie0_mode>;
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;
@ -918,8 +902,8 @@
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>,
<0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
ti,syscon-pcie-id = <&pcie_devid>;
ti,syscon-pcie-mode = <&pcie1_mode>;
ti,syscon-pcie-id = <&scm_conf 0x210>;
ti,syscon-pcie-mode = <&scm_conf 0x4070>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
@ -935,7 +919,7 @@
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie1_mode>;
ti,syscon-pcie-mode = <&scm_conf 0x4070>;
num-ib-windows = <16>;
num-ob-windows = <16>;
max-link-speed = <2>;

19
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
View File

@ -227,7 +227,22 @@
};
};
m_can0: mcan@40528000 {
secure_proxy_mcu: mailbox@2a480000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x0 0x2a480000 0x0 0x80000>,
<0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
m_can0: can@40528000 {
compatible = "bosch,m_can";
reg = <0x0 0x40528000 0x0 0x400>,
<0x0 0x40500000 0x0 0x4400>;
@ -243,7 +258,7 @@
status = "disabled";
};
m_can1: mcan@40568000 {
m_can1: can@40568000 {
compatible = "bosch,m_can";
reg = <0x0 0x40568000 0x0 0x400>,
<0x0 0x40540000 0x0 0x4400>;

17
arch/arm64/boot/dts/ti/k3-am65.dtsi
View File

@ -19,23 +19,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &main_i2c0;
i2c3 = &main_i2c1;
i2c4 = &main_i2c2;
i2c5 = &main_i2c3;
ethernet0 = &cpsw_port1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
chosen { };
firmware {

2
arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
View File

@ -35,7 +35,7 @@
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */

71
arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso Normal file
View File

@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0
/**
* OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM.
* Panel Link: https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT
* AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM
*
* Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
&{/} {
display0 {
compatible = "rocktech,rk101ii01d-ct";
backlight = <&lcd_bl>;
enable-gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
port {
lcd_in0: endpoint {
remote-endpoint = <&oldi_out0>;
};
};
};
lcd_bl: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels =
<0 32 64 96 128 160 192 224 255>;
default-brightness-level = <8>;
};
};
&dss {
status = "okay";
};
&dss_ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
oldi_out0: endpoint {
remote-endpoint = <&lcd_in0>;
};
};
};
&main_i2c1 {
#address-cells = <1>;
#size-cells = <0>;
touchscreen@14 {
compatible = "goodix,gt928";
reg = <0x14>;
interrupt-parent = <&pca9554>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <1280>;
touchscreen-size-y = <800>;
reset-gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
irq-gpios = <&pca9554 3 GPIO_ACTIVE_HIGH>;
};
};

172
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
View File

@ -13,9 +13,22 @@
compatible = "ti,am654-evm", "ti,am654";
model = "Texas Instruments AM654 Base Board";
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &main_i2c0;
i2c3 = &main_i2c1;
i2c4 = &main_i2c2;
ethernet0 = &cpsw_port1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
chosen {
stdout-path = "serial2:115200n8";
bootargs = "earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
@ -86,7 +99,7 @@
};
};
evm_12v0: fixedregulator-evm12v0 {
evm_12v0: regulator-0 {
/* main supply */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
@ -96,7 +109,7 @@
regulator-boot-on;
};
vcc3v3_io: fixedregulator-vcc3v3io {
vcc3v3_io: regulator-1 {
/* Output of TPS54334 */
compatible = "regulator-fixed";
regulator-name = "vcc3v3_io";
@ -107,7 +120,7 @@
vin-supply = <&evm_12v0>;
};
vdd_mmc1_sd: fixedregulator-sd {
vdd_mmc1_sd: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1_sd";
regulator-min-microvolt = <3300000>;
@ -117,24 +130,53 @@
vin-supply = <&vcc3v3_io>;
gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
};
vtt_supply: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "vtt";
pinctrl-names = "default";
pinctrl-0 = <&ddr_vtt_pins_default>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc3v3_io>;
gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
};
};
&wkup_pmx0 {
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
>;
};
ddr_vtt_pins_default: ddr-vtt-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
>;
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
};
push_button_pins_default: push-button-pins-default {
push_button_pins_default: push-button-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
@ -156,7 +198,16 @@
>;
};
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
>;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
@ -173,16 +224,23 @@
>;
};
mcu_mdio_pins_default: mcu-mdio1-pins-default {
mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */
>;
};
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
@ -191,14 +249,14 @@
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
>;
};
main_spi0_pins_default: main-spi0-pins-default {
main_spi0_pins_default: main-spi0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
@ -207,7 +265,7 @@
>;
};
main_mmc0_pins_default: main-mmc0-pins-default {
main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
@ -224,7 +282,7 @@
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
@ -237,7 +295,7 @@
>;
};
usb1_pins_default: usb1-pins-default {
usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
>;
@ -245,21 +303,21 @@
};
&main_pmx1 {
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
ecap0_pins_default: ecap0-pins-default {
ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
@ -269,11 +327,14 @@
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&mcu_uart0 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart0 {
@ -289,6 +350,25 @@
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
/* AT24CM01 */
compatible = "atmel,24c1024";
reg = <0x50>;
};
vdd_mpu: regulator@60 {
compatible = "ti,tps62363";
reg = <0x60>;
regulator-name = "VDD_MPU";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1770000>;
regulator-always-on;
regulator-boot-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
ti,enable-vout-discharge;
};
pca9554: gpio@39 {
compatible = "nxp,pca9554";
reg = <0x39>;
@ -305,7 +385,9 @@
&mcu_i2c0 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_i2c0 {
@ -438,13 +520,13 @@
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
};
&mcu_r5fss0_core1 {
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
&ospi0 {
@ -462,6 +544,52 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x20000>;
};
partition@6a0000 {
label = "ospi.env.backup";
reg = <0x6a0000 0x20000>;
};
partition@6c0000 {
label = "ospi.sysfw";
reg = <0x6c0000 0x100000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fe0000 {
label = "ospi.phypattern";
reg = <0x3fe0000 0x20000>;
};
};
};
};

1
arch/arm64/boot/dts/ti/k3-am654.dtsi
View File

@ -113,6 +113,7 @@
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
thermal_zones: thermal-zones {

2
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
View File

@ -22,7 +22,7 @@
};
&main_pmx0 {
main_mmc0_pins_default: main-mmc0-pins-default {
main_mmc0_pins_default: main-mmc0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */

24
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
View File

@ -27,7 +27,7 @@
};
&main_pmx0 {
main_m2_enable_pins_default: main-m2-enable-pins-default {
main_m2_enable_pins_default: main-m2-enable-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
>;
@ -39,7 +39,7 @@
>;
};
main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default {
main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
@ -56,7 +56,7 @@
};
&main_pmx1 {
main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default {
main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
@ -66,20 +66,18 @@
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <
&main_m2_pcie_mux_control
&arduino_io_d4_to_d9_pins_default
>;
pinctrl-0 =
<&main_m2_pcie_mux_control>,
<&arduino_io_d4_to_d9_pins_default>;
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <
&main_m2_enable_pins_default
&main_pmx0_m2_config_pins_default
&main_pmx1_m2_config_pins_default
&cp2102n_reset_pin_default
>;
pinctrl-0 =
<&main_m2_enable_pins_default>,
<&main_pmx0_m2_config_pins_default>,
<&main_pmx1_m2_config_pins_default>,
<&cp2102n_reset_pin_default>;
};
/*

171
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
View File

@ -22,6 +22,8 @@
};
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart8;
mmc1 = &main_sdhci1;
can0 = &mcu_mcan0;
@ -122,21 +124,21 @@
};
&main_pmx0 {
main_uart8_pins_default: main-uart8-pins-default {
main_uart8_pins_default: main-uart8-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */
J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
@ -148,78 +150,154 @@
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
>;
};
main_usbss0_pins_default: main-usbss0-pins-default {
main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
};
main_mcan6_pins_default: main-mcan6-pins-default {
main_mcan6_pins_default: main-mcan6-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */
J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */
>;
};
main_mcan7_pins_default: main-mcan7-pins-default {
main_mcan7_pins_default: main-mcan7-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
>;
};
main_i2c4_pins_default: main-i2c4-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */
J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */
>;
};
rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
>;
};
};
&wkup_pmx0 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
&wkup_pmx2 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
};
mcu_mdio_pins_default: mcu-mdio-pins-default {
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
>;
};
mcu_mcan0_pins_default: mcu-mcan0-pins-default {
mcu_mdio_pins_default: mcu-mdio-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
>;
};
mcu_mcan1_pins_default: mcu-mcan1-pins-default {
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
>;
};
mcu_i2c1_pins_default: mcu-i2c1-pins-default {
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
>;
};
mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */
J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */
>;
};
mcu_i2c1_pins_default: mcu-i2c1-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
>;
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
>;
};
};
&wkup_pmx3 {
mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
>;
};
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&rpi_header_gpio0_pins_default>;
};
&main_gpio2 {
@ -235,7 +313,8 @@
};
&wkup_gpio0 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>;
};
&wkup_gpio1 {
@ -244,6 +323,14 @@
&wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart8 {
@ -271,6 +358,20 @@
};
};
&main_i2c4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c4_pins_default>;
clock-frequency = <400000>;
};
&mcu_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_sdhci0 {
/* Unused */
status = "disabled";
@ -287,7 +388,7 @@
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {

22
arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
View File

@ -27,3 +27,25 @@
};
};
};
&wkup_pmx2 {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
>;
};
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@51 {
/* AT24C512C-MAHM-T */
compatible = "atmel,24c512";
reg = <0x51>;
};
};

182
arch/arm64/boot/dts/ti/k3-am69-sk.dts
View File

@ -21,9 +21,14 @@
};
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart8;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
i2c0 = &main_i2c0;
i2c0 = &wkup_i2c0;
i2c3 = &main_i2c0;
ethernet0 = &mcu_cpsw_port1;
};
memory@80000000 {
@ -105,21 +110,21 @@
};
&main_pmx0 {
main_uart8_pins_default: main-uart8-pins-default {
main_uart8_pins_default: main-uart8-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
@ -132,11 +137,147 @@
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */
>;
};
rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */
J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */
J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */
J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */
J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */
J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */
J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */
J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */
J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */
J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */
J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */
J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */
J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */
J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */
>;
};
};
&wkup_pmx2 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
>;
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
>;
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
mcu_i2c0_pins_default: mcu-i2c0-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */
J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */
>;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
>;
};
mcu_mdio_pins_default: mcu-mdio-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
>;
};
mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */
J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */
J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */
J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */
J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */
J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */
J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */
J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */
J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */
>;
};
};
&wkup_pmx3 {
mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */
>;
};
};
&wkup_uart0 {
/* Firmware usage */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@51 {
/* AT24C512C-MAHM-T */
compatible = "atmel,24c512";
reg = <0x51>;
};
};
&wkup_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>;
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&mcu_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_uart8 {
@ -165,6 +306,14 @@
};
};
&main_sdhci0 {
/* eMMC */
status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&main_sdhci1 {
/* SD card */
status = "okay";
@ -177,4 +326,27 @@
&main_gpio0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rpi_header_gpio0_pins_default>;
};
&mcu_cpsw {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
mcu_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
};
};
&mcu_cpsw_port1 {
status = "okay";
phy-mode = "rgmii-rxid";
phy-handle = <&mcu_phy0>;
};

123
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
View File

@ -15,9 +15,18 @@
compatible = "ti,j7200-evm", "ti,j7200";
model = "Texas Instruments J7200 EVM";
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial5 = &main_uart3;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
};
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
evm_12v0: fixedregulator-evm12v0 {
@ -80,48 +89,88 @@
};
};
&wkup_pmx2 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
&wkup_pmx0 {
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */
J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
>;
};
mcu_mdio_pins_default: mcu-mdio1-pins-default {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
>;
};
};
&wkup_pmx2 {
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
wkup_gpio_pins_default: wkup-gpio-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
>;
};
mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
>;
};
};
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */
J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */
>;
};
main_uart3_pins_default: main-uart3-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */
J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
@ -134,7 +183,7 @@
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
>;
@ -142,7 +191,7 @@
};
&main_pmx1 {
main_usbss0_pins_default: main-usbss0-pins-default {
main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
@ -152,22 +201,30 @@
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&mcu_uart0 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
clock-frequency = <96000000>;
};
&main_uart0 {
status = "okay";
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
&main_uart1 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_uart2 {
@ -175,6 +232,13 @@
status = "reserved";
};
&main_uart3 {
/* Shared with MCAN Interface */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart3_pins_default>;
};
&main_gpio2 {
status = "disabled";
};
@ -187,13 +251,18 @@
status = "disabled";
};
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
};
&wkup_gpio1 {
status = "disabled";
};
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {

2
arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
View File

@ -92,7 +92,7 @@
};
&main_pmx0 {
mdio0_pins_default: mdio0-pins-default {
mdio0_pins_default: mdio0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */

264
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
View File

@ -392,6 +392,24 @@
};
};
/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
main_timerio_input: pinctrl@104200 {
compatible = "pinctrl-single";
reg = <0x0 0x104200 0x0 0x50>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x000001ff>;
};
/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
main_timerio_output: pinctrl@104280 {
compatible = "pinctrl-single";
reg = <0x0 0x104280 0x0 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000001f>;
};
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
@ -971,6 +989,246 @@
assigned-clock-parents = <&k3_clks 253 5>;
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 49 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 49 1>;
assigned-clock-parents = <&k3_clks 49 2>;
power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 50 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 51 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 51 1>;
assigned-clock-parents = <&k3_clks 51 2>;
power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 52 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 53 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 53 1>;
assigned-clock-parents = <&k3_clks 53 2>;
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 54 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 55 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 55 1>;
assigned-clock-parents = <&k3_clks 55 2>;
power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 57 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer8: timer@2480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2480000 0x00 0x400>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 58 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 58 1>;
assigned-clock-parents = <&k3_clks 58 2>;
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer9: timer@2490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2490000 0x00 0x400>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 59 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer10: timer@24a0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24a0000 0x00 0x400>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 60 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 60 1>;
assigned-clock-parents = <&k3_clks 60 2>;
power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer11: timer@24b0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24b0000 0x00 0x400>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 62 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer12: timer@24c0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24c0000 0x00 0x400>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 63 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 63 1>;
assigned-clock-parents = <&k3_clks 63 2>;
power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer13: timer@24d0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24d0000 0x00 0x400>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 64 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer14: timer@24e0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24e0000 0x00 0x400>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 65 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 65 1>;
assigned-clock-parents = <&k3_clks 65 2>;
power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer15: timer@24f0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24f0000 0x00 0x400>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 66 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer16: timer@2500000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2500000 0x00 0x400>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 67 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 67 1>;
assigned-clock-parents = <&k3_clks 67 2>;
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer17: timer@2510000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2510000 0x00 0x400>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 68 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer18: timer@2520000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2520000 0x00 0x400>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 69 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 69 1>;
assigned-clock-parents = <&k3_clks 69 2>;
power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer19: timer@2530000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2530000 0x00 0x400>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 70 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j7200-r5fss";
ti,cluster-mode = <1>;
@ -1010,4 +1268,10 @@
ti,loczrama = <1>;
};
};
main_esm: esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <656>, <657>;
};
};

179
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
View File

@ -34,6 +34,136 @@
};
};
mcu_timer0: timer@40400000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40400000 0x00 0x400>;
interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 35 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 35 1>;
assigned-clock-parents = <&k3_clks 35 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer1: timer@40410000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 71 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>;
power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer2: timer@40420000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40420000 0x00 0x400>;
interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 72 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 72 1>;
assigned-clock-parents = <&k3_clks 72 2>;
power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer3: timer@40430000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40430000 0x00 0x400>;
interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 73 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>;
power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer4: timer@40440000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40440000 0x00 0x400>;
interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 74 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 74 1>;
assigned-clock-parents = <&k3_clks 74 2>;
power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer5: timer@40450000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40450000 0x00 0x400>;
interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 75 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer6: timer@40460000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40460000 0x00 0x400>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 76 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 76 1>;
assigned-clock-parents = <&k3_clks 76 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer7: timer@40470000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40470000 0x00 0x400>;
interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 77 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>;
assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer8: timer@40480000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40480000 0x00 0x400>;
interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 78 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 78 1>;
assigned-clock-parents = <&k3_clks 78 2>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_timer9: timer@40490000 {
status = "reserved";
compatible = "ti,am654-timer";
reg = <0x00 0x40490000 0x00 0x400>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 79 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>;
assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
mcu_conf: syscon@40f00000 {
compatible = "syscon", "simple-mfd";
reg = <0x00 0x40f00000 0x00 0x20000>;
@ -53,6 +183,26 @@
reg = <0x00 0x43000014 0x00 0x4>;
};
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
mcu_timerio_input: pinctrl@40f04200 {
compatible = "pinctrl-single";
reg = <0x0 0x40f04200 0x0 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000F>;
status = "reserved";
};
/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
mcu_timerio_output: pinctrl@40f04280 {
compatible = "pinctrl-single";
reg = <0x0 0x40f04280 0x0 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000F>;
status = "reserved";
};
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
@ -62,7 +212,7 @@
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx1: pinctrl@0x4301c038 {
wkup_pmx1: pinctrl@4301c038 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c038 0x00 0x8>;
@ -71,7 +221,7 @@
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx2: pinctrl@0x4301c068 {
wkup_pmx2: pinctrl@4301c068 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c068 0x00 0xec>;
@ -80,7 +230,7 @@
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx3: pinctrl@0x4301c174 {
wkup_pmx3: pinctrl@4301c174 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c174 0x00 0x20>;
@ -209,6 +359,21 @@
};
};
secure_proxy_mcu: mailbox@2a480000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x0 0x2a480000 0x0 0x80000>,
<0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
@ -459,4 +624,12 @@
status = "disabled"; /* Used by OP-TEE */
};
};
wkup_vtm0: temperature-sensor@42040000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0x42040000 0x00 0x350>,
<0x00 0x42050000 0x00 0x350>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
};

107
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
View File

@ -83,7 +83,7 @@
};
&wkup_pmx0 {
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
@ -101,7 +101,7 @@
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
@ -118,8 +118,17 @@
};
};
&wkup_pmx2 {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>;
};
};
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
@ -140,6 +149,37 @@
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x00 0x00 0x4000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "hbmc.tiboot3";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "hbmc.tispl";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "hbmc.u-boot";
reg = <0x300000 0x400000>;
};
partition@700000 {
label = "hbmc.env";
reg = <0x700000 0x40000>;
};
partition@800000 {
label = "hbmc.rootfs";
reg = <0x800000 0x3800000>;
};
};
};
};
@ -174,25 +214,25 @@
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
@ -214,6 +254,18 @@
};
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
@ -229,5 +281,46 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x100000>;
};
partition@100000 {
label = "ospi.tispl";
reg = <0x100000 0x200000>;
};
partition@300000 {
label = "ospi.u-boot";
reg = <0x300000 0x400000>;
};
partition@700000 {
label = "ospi.env";
reg = <0x700000 0x40000>;
};
partition@740000 {
label = "ospi.env.backup";
reg = <0x740000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};

47
arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi Normal file
View File

@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
thermal_zones: thermal-zones {
mcu_thermal: mcu-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 0>;
trips {
wkup_crit: wkup-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
mpu_thermal: mpu-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 1>;
trips {
mpu_crit: mpu-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main_thermal: main-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 2>;
trips {
c7x_crit: c7x-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
};

21
arch/arm64/boot/dts/ti/k3-j7200.dtsi
View File

@ -18,23 +18,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
serial5 = &main_uart3;
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
serial9 = &main_uart7;
serial10 = &main_uart8;
serial11 = &main_uart9;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
};
chosen { };
cpus {
@ -95,6 +78,7 @@
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
firmware {
@ -128,6 +112,7 @@
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
@ -170,6 +155,8 @@
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
};
};
#include "k3-j7200-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */

157
arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
View File

@ -20,6 +20,7 @@
model = "BeagleBoard.org BeagleBone AI-64";
aliases {
serial0 = &wkup_uart0;
serial2 = &main_uart0;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
@ -304,7 +305,7 @@
};
&main_pmx0 {
led_pins_default: led-pins-default {
led_pins_default: led-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
@ -314,7 +315,7 @@
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
@ -327,64 +328,64 @@
>;
};
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
};
sd_pwr_en_pins_default: sd-pwr-en-pins-default {
sd_pwr_en_pins_default: sd-pwr-en-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
>;
};
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
>;
};
main_usbss0_pins_default: main-usbss0-pins-default {
main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
>;
};
main_usbss1_pins_default: main-usbss1-pins-default {
main_usbss1_pins_default: main-usbss1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
>;
};
dp0_3v3_en_pins_default:dp0-3v3-en-pins-default {
dp0_3v3_en_pins_default:dp0-3v3-en-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
>;
};
dp0_pins_default: dp0-pins-default {
dp0_pins_default: dp0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
>;
};
main_i2c2_pins_default: main-i2c2-pins-default {
main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */
J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */
@ -393,14 +394,14 @@
>;
};
main_i2c3_pins_default: main-i2c3-pins-default {
main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
>;
};
main_i2c4_pins_default: main-i2c4-pins-default {
main_i2c4_pins_default: main-i2c4-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */
J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */
@ -409,14 +410,14 @@
>;
};
main_i2c5_pins_default: main-i2c5-pins-default {
main_i2c5_pins_default: main-i2c5-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
>;
};
main_i2c6_pins_default: main-i2c6-pins-default {
main_i2c6_pins_default: main-i2c6-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
@ -425,21 +426,21 @@
>;
};
csi0_gpio_pins_default: csi0-gpio-pins-default {
csi0_gpio_pins_default: csi0-gpio-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
>;
};
csi1_gpio_pins_default: csi1-gpio-pins-default {
csi1_gpio_pins_default: csi1-gpio-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
>;
};
pcie1_rst_pins_default: pcie1-rst-pins-default {
pcie1_rst_pins_default: pcie1-rst-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
>;
@ -447,13 +448,13 @@
};
&wkup_pmx0 {
eeprom_wp_pins_default: eeprom-wp-pins-default {
eeprom_wp_pins_default: eeprom-wp-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
>;
};
mcu_adc0_pins_default: mcu-adc0-pins-default {
mcu_adc0_pins_default: mcu-adc0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
@ -465,13 +466,13 @@
>;
};
mcu_adc1_pins_default: mcu-adc1-pins-default {
mcu_adc1_pins_default: mcu-adc1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
>;
};
mikro_bus_pins_default: mikro-bus-pins-default {
mikro_bus_pins_default: mikro-bus-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
@ -494,7 +495,7 @@
>;
};
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
@ -511,27 +512,34 @@
>;
};
mcu_mdio_pins_default: mcu-mdio1-pins-default {
mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
>;
};
sw_pwr_pins_default: sw-pwr-pins-default {
sw_pwr_pins_default: sw-pwr-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
>;
};
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
};
mcu_usbss1_pins_default: mcu-usbss1-pins-default {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
>;
};
mcu_usbss1_pins_default: mcu-usbss1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
>;
@ -541,6 +549,8 @@
&wkup_uart0 {
/* Wakeup UART is used by TIFS firmware. */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&main_uart0 {
@ -593,7 +603,7 @@
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>;
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
@ -623,7 +633,7 @@
&main_i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>;
pinctrl-0 = <&main_i2c5_pins_default>;
clock-frequency = <400000>;
};
@ -639,12 +649,14 @@
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>;
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&eeprom_wp_pins_default>;
};
};
@ -680,7 +692,8 @@
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>;
pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
<&mikro_bus_pins_default>;
};
&wkup_gpio1 {
@ -688,6 +701,11 @@
status = "disabled";
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>;
};
&usb_serdes_mux {
idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
};
@ -759,7 +777,7 @@
&usbss1 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>;
pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>;
ti,vbus-divider;
};
@ -872,12 +890,8 @@
};
};
&pcie0_rc {
/* Unused */
status = "disabled";
};
&pcie1_rc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_rst_pins_default>;
phys = <&serdes1_pcie_link>;
@ -887,55 +901,12 @@
reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
};
&pcie2_rc {
/* Unused */
status = "disabled";
};
&pcie0_ep {
status = "disabled";
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&pcie1_ep {
status = "disabled";
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
&pcie2_ep {
/* Unused */
status = "disabled";
};
&pcie3_rc {
/* Unused */
status = "disabled";
};
&pcie3_ep {
/* Unused */
status = "disabled";
};
&icssg0_mdio {
/* Unused */
status = "disabled";
};
&icssg1_mdio {
/* Unused */
status = "disabled";
};
&ufs_wrapper {
status = "disabled";
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@ -950,6 +921,7 @@
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
@ -964,6 +936,7 @@
};
&mailbox0_cluster2 {
status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
@ -978,6 +951,7 @@
};
&mailbox0_cluster3 {
status = "okay";
interrupts = <424>;
mbox_c66_0: mbox-c66-0 {
@ -992,6 +966,7 @@
};
&mailbox0_cluster4 {
status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
@ -1001,55 +976,55 @@
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};

226
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
View File

@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*
* Product Link: https://www.ti.com/tool/J721EXCPXEVM
*/
/dts-v1/;
@ -15,16 +17,27 @@
compatible = "ti,j721e-evm", "ti,j721e";
model = "Texas Instruments J721e EVM";
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
serial6 = &main_uart4;
ethernet0 = &cpsw_port1;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
};
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;
sw10: switch-10 {
label = "GPIO Key USER1";
@ -173,13 +186,43 @@
};
&main_pmx0 {
sw10_button_pins_default: sw10-button-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
>;
};
main_uart2_pins_default: main-uart2-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */
J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */
>;
};
main_uart4_pins_default: main-uart4-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */
J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */
>;
};
sw10_button_pins_default: sw10-button-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
@ -193,66 +236,66 @@
>;
};
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
>;
};
main_usbss0_pins_default: main-usbss0-pins-default {
main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
};
main_usbss1_pins_default: main-usbss1-pins-default {
main_usbss1_pins_default: main-usbss1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
};
dp0_pins_default: dp0-pins-default {
dp0_pins_default: dp0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
>;
};
main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
>;
};
main_i2c3_pins_default: main-i2c3-pins-default {
main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
>;
};
main_i2c6_pins_default: main-i2c6-pins-default {
main_i2c6_pins_default: main-i2c6-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
>;
};
mcasp10_pins_default: mcasp10-pins-default {
mcasp10_pins_default: mcasp10-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
@ -266,27 +309,27 @@
>;
};
audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
>;
};
main_mcan0_pins_default: main-mcan0-pins-default {
main_mcan0_pins_default: main-mcan0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
>;
};
main_mcan2_pins_default: main-mcan2-pins-default {
main_mcan2_pins_default: main-mcan2-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
>;
};
main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
>;
@ -294,13 +337,29 @@
};
&wkup_pmx0 {
sw11_button_pins_default: sw11-button-pins-default {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
>;
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
sw11_button_pins_default: sw11-button-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
>;
};
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
@ -313,7 +372,7 @@
>;
};
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
@ -330,70 +389,84 @@
>;
};
mcu_mdio_pins_default: mcu-mdio1-pins-default {
mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
>;
};
mcu_mcan0_pins_default: mcu-mcan0-pins-default {
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
>;
};
mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
>;
};
mcu_mcan1_pins_default: mcu-mcan1-pins-default {
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
>;
};
mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
>;
};
wkup_gpio_pins_default: wkup-gpio-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
>;
};
};
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&mcu_uart0 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
/* Shared with ATF on this platform */
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&main_uart1 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_uart2 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&main_uart2_pins_default>;
};
&main_uart4 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&main_uart4_pins_default>;
};
&main_gpio2 {
@ -420,6 +493,11 @@
status = "disabled";
};
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
};
&wkup_gpio1 {
status = "disabled";
};
@ -513,6 +591,52 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "qspi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "qspi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "qspi.env";
reg = <0x680000 0x20000>;
};
partition@6a0000 {
label = "qspi.env.backup";
reg = <0x6a0000 0x20000>;
};
partition@6c0000 {
label = "qspi.sysfw";
reg = <0x6c0000 0x100000>;
};
partition@800000 {
label = "qspi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fe0000 {
label = "qspi.phypattern";
reg = <0x3fe0000 0x20000>;
};
};
};
};
@ -646,7 +770,7 @@
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@ -820,6 +944,7 @@
};
&pcie0_rc {
status = "okay";
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
@ -827,6 +952,7 @@
};
&pcie1_rc {
status = "okay";
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
@ -834,49 +960,13 @@
};
&pcie2_rc {
status = "okay";
reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
phys = <&serdes2_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
&pcie0_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
status = "disabled";
};
&pcie1_ep {
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
status = "disabled";
};
&pcie2_ep {
phys = <&serdes2_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
status = "disabled";
};
&pcie3_rc {
status = "disabled";
};
&pcie3_ep {
status = "disabled";
};
&icssg0_mdio {
status = "disabled";
};
&icssg1_mdio {
status = "disabled";
};
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";

2
arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
View File

@ -94,7 +94,7 @@
};
&main_pmx0 {
mdio0_pins_default: mdio0-pins-default {
mdio0_pins_default: mdio0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */

362
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
View File

@ -548,6 +548,24 @@
pinctrl-single,function-mask = <0xffffffff>;
};
/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
main_timerio_input: pinctrl@104200 {
compatible = "pinctrl-single";
reg = <0x00 0x104200 0x00 0x50>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000007>;
};
/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
main_timerio_output: pinctrl@104280 {
compatible = "pinctrl-single";
reg = <0x00 0x104280 0x00 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000001f>;
};
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
@ -814,26 +832,7 @@
ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
<0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};
pcie0_ep: pcie-ep@2900000 {
compatible = "ti,j721e-pcie-ep";
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
status = "disabled";
};
pcie1_rc: pcie@2910000 {
@ -862,26 +861,7 @@
ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};
pcie1_ep: pcie-ep@2910000 {
compatible = "ti,j721e-pcie-ep";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x00 0x18000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
status = "disabled";
};
pcie2_rc: pcie@2920000 {
@ -910,26 +890,7 @@
ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
<0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};
pcie2_ep: pcie-ep@2920000 {
compatible = "ti,j721e-pcie-ep";
reg = <0x00 0x02920000 0x00 0x1000>,
<0x00 0x02927000 0x00 0x400>,
<0x00 0x0e000000 0x00 0x00800000>,
<0x44 0x00000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 241 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
status = "disabled";
};
pcie3_rc: pcie@2930000 {
@ -958,28 +919,7 @@
ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
<0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
};
pcie3_ep: pcie-ep@2930000 {
compatible = "ti,j721e-pcie-ep";
reg = <0x00 0x02930000 0x00 0x1000>,
<0x00 0x02937000 0x00 0x400>,
<0x00 0x0e800000 0x00 0x00800000>,
<0x44 0x10000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 242 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
};
serdes_wiz4: wiz@5050000 {
@ -1023,6 +963,246 @@
};
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 49 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 49 1>;
assigned-clock-parents = <&k3_clks 49 2>;
power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 50 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 51 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 51 1>;
assigned-clock-parents = <&k3_clks 51 2>;
power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 52 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 53 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 53 1>;
assigned-clock-parents = <&k3_clks 53 2>;
power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 54 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 55 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 55 1>;
assigned-clock-parents = <&k3_clks 55 2>;
power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 57 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer8: timer@2480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2480000 0x00 0x400>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 58 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 58 1>;
assigned-clock-parents = <&k3_clks 58 2>;
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer9: timer@2490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2490000 0x00 0x400>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 59 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer10: timer@24a0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24a0000 0x00 0x400>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 60 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 60 1>;
assigned-clock-parents = <&k3_clks 60 2>;
power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer11: timer@24b0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24b0000 0x00 0x400>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 62 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer12: timer@24c0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24c0000 0x00 0x400>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 63 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 63 1>;
assigned-clock-parents = <&k3_clks 63 2>;
power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer13: timer@24d0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24d0000 0x00 0x400>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 64 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer14: timer@24e0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24e0000 0x00 0x400>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 65 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 65 1>;
assigned-clock-parents = <&k3_clks 65 2>;
power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer15: timer@24f0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24f0000 0x00 0x400>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 66 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer16: timer@2500000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2500000 0x00 0x400>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 67 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 67 1>;
assigned-clock-parents = <&k3_clks 67 2>;
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer17: timer@2510000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2510000 0x00 0x400>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 68 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer18: timer@2520000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2520000 0x00 0x400>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 69 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 69 1>;
assigned-clock-parents = <&k3_clks 69 2>;
power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer19: timer@2530000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2530000 0x00 0x400>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 70 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@ -1287,8 +1467,8 @@
bus-width = <8>;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
ti,otap-del-sel-legacy = <0xf>;
ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
ti,otap-del-sel-hs400 = <0x0>;
@ -1309,11 +1489,12 @@
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0xf>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
@ -1335,11 +1516,12 @@
assigned-clocks = <&k3_clks 93 0>;
assigned-clock-parents = <&k3_clks 93 1>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0xf>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
@ -2091,6 +2273,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
status = "disabled";
};
};
@ -2232,6 +2415,7 @@
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
status = "disabled";
};
};
@ -2532,4 +2716,10 @@
clocks = <&k3_clks 273 1>;
status = "disabled";
};
main_esm: esm@700000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <344>, <345>;
};
};

206
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
View File

@ -62,6 +62,28 @@
pinctrl-single,function-mask = <0xffffffff>;
};
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
mcu_timerio_input: pinctrl@40f04200 {
compatible = "pinctrl-single";
reg = <0x00 0x40f04200 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Non-MPU Firmware usage */
status = "reserved";
};
/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
mcu_timerio_output: pinctrl@40f04280 {
compatible = "pinctrl-single";
reg = <0x00 0x40f04280 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
@ -70,6 +92,145 @@
#size-cells = <1>;
};
mcu_timer0: timer@40400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40400000 0x00 0x400>;
interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 35 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 35 1>;
assigned-clock-parents = <&k3_clks 35 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer1: timer@40410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 71 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>;
assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>;
power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer2: timer@40420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40420000 0x00 0x400>;
interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 72 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 72 1>;
assigned-clock-parents = <&k3_clks 72 2>;
power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer3: timer@40430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40430000 0x00 0x400>;
interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 73 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>;
assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>;
power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer4: timer@40440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40440000 0x00 0x400>;
interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 74 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 74 1>;
assigned-clock-parents = <&k3_clks 74 2>;
power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer5: timer@40450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40450000 0x00 0x400>;
interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 75 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>;
assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer6: timer@40460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40460000 0x00 0x400>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 76 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 76 1>;
assigned-clock-parents = <&k3_clks 76 2>;
power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer7: timer@40470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40470000 0x00 0x400>;
interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 77 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>;
assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer8: timer@40480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40480000 0x00 0x400>;
interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 78 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 78 1>;
assigned-clock-parents = <&k3_clks 78 2>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer9: timer@40490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40490000 0x00 0x400>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 79 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>;
assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
@ -181,6 +342,27 @@
#size-cells = <2>;
ranges;
hbmc_mux: mux-controller@47000004 {
compatible = "reg-mux";
reg = <0x00 0x47000004 0x00 0x2>;
#mux-control-cells = <1>;
mux-reg-masks = <0x4 0x2>; /* HBMC select */
};
hbmc: hyperbus@47034000 {
compatible = "ti,am654-hbmc";
reg = <0x00 0x47034000 0x00 0x100>,
<0x05 0x00000000 0x01 0x0000000>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 102 0>;
assigned-clocks = <&k3_clks 102 5>;
assigned-clock-rates = <333333333>;
#address-cells = <2>;
#size-cells = <1>;
mux-controls = <&hbmc_mux 0>;
status = "disabled";
};
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
@ -296,6 +478,21 @@
};
};
secure_proxy_mcu: mailbox@2a480000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x0 0x2a480000 0x0 0x80000>,
<0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
@ -458,4 +655,13 @@
clocks = <&k3_clks 276 0>;
status = "disabled";
};
wkup_vtm0: temperature-sensor@42040000 {
compatible = "ti,j721e-vtm";
reg = <0x00 0x42040000 0x00 0x350>,
<0x00 0x42050000 0x00 0x350>,
<0x00 0x43000300 0x00 0x10>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
};

210
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
View File

@ -16,9 +16,17 @@
compatible = "ti,j721e-sk", "ti,j721e";
model = "Texas Instruments J721E SK";
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
ethernet0 = &cpsw_port1;
mmc1 = &main_sdhci1;
};
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
@ -281,7 +289,7 @@
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
@ -294,7 +302,7 @@
>;
};
main_uart0_pins_default: main-uart0-pins-default {
main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
@ -303,53 +311,60 @@
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
>;
};
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
>;
};
main_i2c3_pins_default: main-i2c3-pins-default {
main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
>;
};
main_usbss0_pins_default: main-usbss0-pins-default {
main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
};
main_usbss1_pins_default: main-usbss1-pins-default {
main_usbss1_pins_default: main-usbss1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
};
dp0_pins_default: dp0-pins-default {
dp0_pins_default: dp0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
>;
};
dp_pwr_en_pins_default: dp-pwr-en-pins-default {
dp_pwr_en_pins_default: dp-pwr-en-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
>;
};
dss_vout0_pins_default: dss-vout0-pins-default {
dss_vout0_pins_default: dss-vout0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
@ -382,33 +397,33 @@
>;
};
hdmi_hpd_pins_default: hdmi-hpd-pins-default {
hdmi_hpd_pins_default: hdmi-hpd-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
>;
};
hdmi_pdn_pins_default: hdmi-pdn-pins-default {
hdmi_pdn_pins_default: hdmi-pdn-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
>;
};
/* Reset for M.2 E Key slot on PCIe0 */
ekey_reset_pins_default: ekey-reset-pns-pins-default {
ekey_reset_pins_default: ekey-reset-pns-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
>;
};
main_i2c5_pins_default: main-i2c5-pins-default {
main_i2c5_pins_default: main-i2c5-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
>;
};
rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default {
rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
@ -436,7 +451,7 @@
>;
};
rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default {
rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
>;
@ -444,7 +459,7 @@
};
&wkup_pmx0 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
@ -461,14 +476,14 @@
>;
};
mcu_mdio_pins_default: mcu-mdio1-pins-default {
mcu_mdio_pins_default: mcu-mdio1-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
@ -484,19 +499,35 @@
>;
};
vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
>;
};
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
>;
};
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
>;
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
@ -504,7 +535,7 @@
};
/* Reset for M.2 M Key slot on PCIe1 */
mkey_reset_pins_default: mkey-reset-pns-pins-default {
mkey_reset_pins_default: mkey-reset-pns-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
>;
@ -514,11 +545,27 @@
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@51 {
/* AT24C512C-MAHM-T */
compatible = "atmel,24c512";
reg = <0x51>;
};
};
&mcu_uart0 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart0 {
@ -531,7 +578,8 @@
&main_uart1 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&main_sdhci0 {
@ -569,6 +617,52 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "ospi.sysfw";
reg = <0x6c0000 0x100000>;
};
partition@7c0000 {
label = "ospi.env.backup";
reg = <0x7c0000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
@ -781,7 +875,7 @@
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@ -872,6 +966,7 @@
};
&pcie0_rc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ekey_reset_pins_default>;
reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
@ -882,6 +977,7 @@
};
&pcie1_rc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mkey_reset_pins_default>;
reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
@ -891,48 +987,6 @@
num-lanes = <2>;
};
&pcie2_rc {
/* Unused */
status = "disabled";
};
&pcie0_ep {
status = "disabled";
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&pcie1_ep {
status = "disabled";
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
&pcie2_ep {
/* Unused */
status = "disabled";
};
&pcie3_rc {
/* Unused */
status = "disabled";
};
&pcie3_ep {
/* Unused */
status = "disabled";
};
&icssg0_mdio {
status = "disabled";
};
&icssg1_mdio {
status = "disabled";
};
&ufs_wrapper {
status = "disabled";
};
@ -1008,55 +1062,55 @@
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};

167
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
View File

@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
*
* Product Link: https://www.ti.com/tool/J721EXSOMXEVM
*/
/dts-v1/;
@ -143,14 +145,14 @@
};
&wkup_pmx0 {
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */
@ -165,6 +167,51 @@
J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
>;
};
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */
>;
};
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
/* CAV24C256WE-GT3 */
compatible = "atmel,24c256";
reg = <0x50>;
};
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
/* CAV24C256WE-GT3 */
compatible = "atmel,24c256";
reg = <0x50>;
};
};
&ospi0 {
@ -182,6 +229,104 @@
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x20000>;
};
partition@6a0000 {
label = "ospi.env.backup";
reg = <0x6a0000 0x20000>;
};
partition@6c0000 {
label = "ospi.sysfw";
reg = <0x6c0000 0x100000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fe0000 {
label = "ospi.phypattern";
reg = <0x3fe0000 0x20000>;
};
};
};
};
&hbmc {
/* OSPI and HBMC are muxed inside FSS, Bootloader will enable
* appropriate node based on board detection
*/
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
<0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x00 0x00 0x4000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "hbmc.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "hbmc.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "hbmc.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "hbmc.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "hbmc.sysfw";
reg = <0x6c0000 0x100000>;
};
partition@800000 {
label = "hbmc.rootfs";
reg = <0x800000 0x3800000>;
};
};
};
};
@ -256,55 +401,55 @@
};
&mcu_r5fss0_core0 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&c66_0 {
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
memory-region = <&c66_0_dma_memory_region>,
<&c66_0_memory_region>;
};
&c66_1 {
mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
memory-region = <&c66_1_dma_memory_region>,
<&c66_1_memory_region>;
};
&c71_0 {
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};

75
arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi Normal file
View File

@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
thermal_zones: thermal-zones {
wkup_thermal: wkup-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 0>;
trips {
wkup_crit: wkup-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
mpu_thermal: mpu-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 1>;
trips {
mpu_crit: mpu-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
c7x_thermal: c7x-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 2>;
trips {
c7x_crit: c7x-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
gpu_thermal: gpu-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 3>;
trips {
gpu_crit: gpu-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
r5f_thermal: r5f-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 4>;
trips {
r5f_crit: r5f-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
};

23
arch/arm64/boot/dts/ti/k3-j721e.dtsi
View File

@ -18,25 +18,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
serial5 = &main_uart3;
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
serial9 = &main_uart7;
serial10 = &main_uart8;
serial11 = &main_uart9;
ethernet0 = &cpsw_port1;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
mmc2 = &main_sdhci2;
};
chosen { };
cpus {
@ -97,6 +78,7 @@
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
firmware {
@ -131,6 +113,7 @@
#size-cells = <2>;
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
<0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
@ -184,6 +167,8 @@
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
};
};
#include "k3-j721e-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */

213
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
View File

@ -9,6 +9,9 @@
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
@ -16,7 +19,6 @@
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,2880000";
};
aliases {
@ -110,7 +112,7 @@
};
&main_pmx0 {
main_uart8_pins_default: main-uart8-pins-default {
main_uart8_pins_default: main-uart8-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
@ -119,14 +121,14 @@
>;
};
main_i2c3_pins_default: main-i2c3-pins-default {
main_i2c3_pins_default: main-i2c3-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */
J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
@ -139,88 +141,126 @@
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
main_usbss0_pins_default: main-usbss0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>;
};
};
&wkup_pmx0 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
&wkup_pmx2 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>;
};
mcu_mdio_pins_default: mcu-mdio-pins-default {
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
mcu_mcan0_pins_default: mcu-mcan0-pins-default {
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
>;
};
mcu_mcan1_pins_default: mcu-mcan1-pins-default {
mcu_mdio_pins_default: mcu-mdio-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
>;
};
mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
mcu_mcan0_pins_default: mcu-mcan0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
>;
};
mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
mcu_mcan1_pins_default: mcu-mcan1-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */
>;
};
mcu_adc0_pins_default: mcu-adc0-pins-default {
mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */
J721S2_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */
J721S2_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */
J721S2_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */
J721S2_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */
J721S2_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */
J721S2_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */
J721S2_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */
J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */
>;
};
mcu_adc1_pins_default: mcu-adc1-pins-default {
mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */
J721S2_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */
J721S2_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */
J721S2_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */
J721S2_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */
J721S2_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */
J721S2_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */
J721S2_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */
J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */
>;
};
mcu_adc0_pins_default: mcu-adc0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */
J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */
J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */
J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */
J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */
J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */
J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */
J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */
>;
};
mcu_adc1_pins_default: mcu-adc1-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */
J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */
J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */
J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */
J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */
J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */
J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */
J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */
>;
};
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>;
};
};
@ -243,11 +283,14 @@
&wkup_uart0 {
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&mcu_uart0 {
status = "okay";
/* Default pinmux */
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart8 {
@ -305,7 +348,7 @@
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
};
&davinci_mdio {
@ -322,6 +365,70 @@
phy-handle = <&phy0>;
};
&serdes_ln_ctrl {
idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
<J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
};
&serdes_refclk {
clock-frequency = <100000000>;
};
&serdes0 {
status = "okay";
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&usb_serdes_mux {
idle-states = <1>; /* USB0 to SERDES lane 1 */
};
&usbss0 {
status = "okay";
pinctrl-0 = <&main_usbss0_pins_default>;
pinctrl-names = "default";
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
};
&ospi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
};
};
&pcie1_rc {
status = "okay";
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
};
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";

405
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
View File

@ -5,6 +5,17 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>
/ {
serdes_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@ -26,6 +37,29 @@
};
};
scm_conf: syscon@104000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00 0x00104000 0x00 0x18000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00104000 0x18000>;
usb_serdes_mux: mux-controller@0 {
compatible = "mmio-mux";
reg = <0x0 0x4>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
serdes_ln_ctrl: mux-controller@80 {
compatible = "mmio-mux";
reg = <0x80 0x10>;
#mux-control-cells = <1>;
mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
<0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@ -72,6 +106,24 @@
pinctrl-single,function-mask = <0xffffffff>;
};
/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
main_timerio_input: pinctrl@104200 {
compatible = "pinctrl-single";
reg = <0x00 0x104200 0x00 0x50>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000007>;
};
/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
main_timerio_output: pinctrl@104280 {
compatible = "pinctrl-single";
reg = <0x00 0x104280 0x00 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000001f>;
};
main_crypto: crypto@4e00000 {
compatible = "ti,j721e-sa2ul";
reg = <0x00 0x04e00000 0x00 0x1200>;
@ -91,6 +143,246 @@
};
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 63 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 63 1>;
assigned-clock-parents = <&k3_clks 63 2>;
power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 64 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 64 1>;
assigned-clock-parents = <&k3_clks 64 2>;
power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 65 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 65 1>;
assigned-clock-parents = <&k3_clks 65 2>;
power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 66 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 66 1>;
assigned-clock-parents = <&k3_clks 66 2>;
power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 67 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 67 1>;
assigned-clock-parents = <&k3_clks 67 2>;
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 68 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 68 1>;
assigned-clock-parents = <&k3_clks 68 2>;
power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 69 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 69 1>;
assigned-clock-parents = <&k3_clks 69 2>;
power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 70 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 70 1>;
assigned-clock-parents = <&k3_clks 70 2>;
power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer8: timer@2480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2480000 0x00 0x400>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 71 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 71 1>;
assigned-clock-parents = <&k3_clks 71 2>;
power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer9: timer@2490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2490000 0x00 0x400>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 72 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 72 1>;
assigned-clock-parents = <&k3_clks 72 2>;
power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer10: timer@24a0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24a0000 0x00 0x400>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 73 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 73 1>;
assigned-clock-parents = <&k3_clks 73 2>;
power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer11: timer@24b0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24b0000 0x00 0x400>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 74 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 74 1>;
assigned-clock-parents = <&k3_clks 74 2>;
power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer12: timer@24c0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24c0000 0x00 0x400>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 75 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 75 1>;
assigned-clock-parents = <&k3_clks 75 2>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer13: timer@24d0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24d0000 0x00 0x400>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 76 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 76 1>;
assigned-clock-parents = <&k3_clks 76 2>;
power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer14: timer@24e0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24e0000 0x00 0x400>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 77 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 77 1>;
assigned-clock-parents = <&k3_clks 77 2>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer15: timer@24f0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24f0000 0x00 0x400>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 78 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 78 1>;
assigned-clock-parents = <&k3_clks 78 2>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer16: timer@2500000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2500000 0x00 0x400>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 79 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 79 1>;
assigned-clock-parents = <&k3_clks 79 2>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer17: timer@2510000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2510000 0x00 0x400>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 80 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 80 1>;
assigned-clock-parents = <&k3_clks 80 2>;
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer18: timer@2520000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2520000 0x00 0x400>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 81 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 81 1>;
assigned-clock-parents = <&k3_clks 81 2>;
power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer19: timer@2530000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2530000 0x00 0x400>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 82 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 82 1>;
assigned-clock-parents = <&k3_clks 82 2>;
power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
@ -738,6 +1030,8 @@
reg-names = "cpts";
clocks = <&k3_clks 226 5>;
clock-names = "cpts";
assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
@ -745,6 +1039,117 @@
};
};
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x04104000 0x00 0x100>;
clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
clock-names = "ref", "lpm";
assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 360 17>;
power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-coherent;
status = "disabled"; /* Needs pinmux */
usb0: usb@6000000 {
compatible = "cdns,usb3";
reg = <0x00 0x06000000 0x00 0x10000>,
<0x00 0x06010000 0x00 0x10000>,
<0x00 0x06020000 0x00 0x10000>;
reg-names = "otg", "xhci", "dev";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host", "peripheral", "otg";
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
serdes_wiz0: wiz@5060000 {
compatible = "ti,j721s2-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
num-lanes = <4>;
#reset-cells = <1>;
#clock-cells = <1>;
ranges = <0x5060000 0x0 0x5060000 0x10000>;
assigned-clocks = <&k3_clks 365 3>;
assigned-clock-parents = <&k3_clks 365 7>;
serdes0: serdes@5060000 {
compatible = "ti,j721e-serdes-10g";
reg = <0x05060000 0x00010000>;
reg-names = "torrent_phy";
resets = <&serdes_wiz0 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
clock-names = "refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
assigned-clock-parents = <&k3_clks 365 3>,
<&k3_clks 365 3>,
<&k3_clks 365 3>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
status = "disabled"; /* Needs lane config */
};
};
pcie1_rc: pcie@2910000 {
compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x800000>,
<0x00 0x18000000 0x00 0x1000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 276 41>;
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb013>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
<0 0 0 2 &pcie1_intc 0>, /* INT B */
<0 0 0 3 &pcie1_intc 0>, /* INT C */
<0 0 0 4 &pcie1_intc 0>; /* INT D */
status = "disabled"; /* Needs gpio and serdes info */
pcie1_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
};
};
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,

275
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
View File

@ -39,6 +39,21 @@
reg = <0x00 0x43000014 0x00 0x4>;
};
secure_proxy_sa3: mailbox@43600000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x43600000 0x00 0x10000>,
<0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
@ -50,12 +65,61 @@
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x178>;
reg = <0x00 0x4301c000 0x00 0x034>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx1: pinctrl@4301c038 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c038 0x00 0x02C>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx2: pinctrl@4301c068 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c068 0x00 0x120>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx3: pinctrl@4301c190 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c190 0x00 0x004>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
mcu_timerio_input: pinctrl@40f04200 {
compatible = "pinctrl-single";
reg = <0x00 0x40f04200 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Non-MPU Firmware usage */
status = "reserved";
};
/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
mcu_timerio_output: pinctrl@40f04280 {
compatible = "pinctrl-single";
reg = <0x00 0x40f04280 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Non-MPU Firmware usage */
status = "reserved";
};
wkup_gpio_intr: interrupt-controller@42200000 {
compatible = "ti,sci-intr";
reg = <0x00 0x42200000 0x00 0x400>;
@ -83,6 +147,146 @@
};
mcu_timer0: timer@40400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40400000 0x00 0x400>;
interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 35 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 35 1>;
assigned-clock-parents = <&k3_clks 35 2>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer1: timer@40410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 83 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 83 1>;
assigned-clock-parents = <&k3_clks 83 2>;
power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer2: timer@40420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40420000 0x00 0x400>;
interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 84 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 84 1>;
assigned-clock-parents = <&k3_clks 84 2>;
power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer3: timer@40430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40430000 0x00 0x400>;
interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 85 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 85 1>;
assigned-clock-parents = <&k3_clks 85 2>;
power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer4: timer@40440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40440000 0x00 0x400>;
interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 86 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 86 1>;
assigned-clock-parents = <&k3_clks 86 2>;
power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer5: timer@40450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40450000 0x00 0x400>;
interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 87 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 87 1>;
assigned-clock-parents = <&k3_clks 87 2>;
power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer6: timer@40460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40460000 0x00 0x400>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 88 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 88 1>;
assigned-clock-parents = <&k3_clks 88 2>;
power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer7: timer@40470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40470000 0x00 0x400>;
interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 89 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 89 1>;
assigned-clock-parents = <&k3_clks 89 2>;
power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer8: timer@40480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40480000 0x00 0x400>;
interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 90 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 90 1>;
assigned-clock-parents = <&k3_clks 90 2>;
power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer9: timer@40490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40490000 0x00 0x400>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 91 1>;
clock-names = "fck";
assigned-clocks = <&k3_clks 91 1>;
assigned-clock-parents = <&k3_clks 91 2>;
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x200>;
@ -280,6 +484,21 @@
};
};
secure_proxy_mcu: mailbox@2a480000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x2a480000 0x00 0x80000>,
<0x00 0x2a380000 0x00 0x80000>,
<0x00 0x2a400000 0x00 0x80000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
@ -333,6 +552,8 @@
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 29 3>;
clock-names = "cpts";
assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */
assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
@ -379,4 +600,56 @@
compatible = "ti,am3359-adc";
};
};
fss: bus@47000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47040000 0x00 0x100>,
<0x05 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 109 5>;
assigned-clocks = <&k3_clks 109 5>;
assigned-clock-parents = <&k3_clks 109 7>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; /* Needs pinmux */
};
ospi1: spi@47050000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47050000 0x00 0x100>,
<0x07 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 110 5>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; /* Needs pinmux */
};
};
wkup_vtm0: temperature-sensor@42040000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0x42040000 0x0 0x350>,
<0x00 0x42050000 0x0 0x350>;
power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
};

67
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
View File

@ -39,15 +39,46 @@
};
};
&wkup_pmx0 {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */
J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */
J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
>;
};
};
&wkup_pmx2 {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
>;
};
};
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
>;
};
main_mcan16_pins_default: main-mcan16-pins-default {
main_mcan16_pins_default: main-mcan16-default-pins {
pinctrl-single,pins = <
J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
@ -55,6 +86,19 @@
};
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
/* CAV24C256WE-GT3 */
compatible = "atmel,24c256";
reg = <0x50>;
};
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
@ -79,3 +123,22 @@
pinctrl-names = "default";
phys = <&transceiver0>;
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
};
};

101
arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi Normal file
View File

@ -0,0 +1,101 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
wkup0_thermal: wkup0-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 0>;
trips {
wkup0_crit: wkup0-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
wkup1_thermal: wkup1-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 1>;
trips {
wkup1_crit: wkup1-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main0_thermal: main0-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 2>;
trips {
main0_crit: main0-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main1_thermal: main1-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 3>;
trips {
main1_crit: main1-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main2_thermal: main2-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 4>;
trips {
main2_crit: main2-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main3_thermal: main3-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 5>;
trips {
main3_crit: main3-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main4_thermal: main4-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 6>;
trips {
main4_crit: main4-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};

7
arch/arm64/boot/dts/ti/k3-j721s2.dtsi
View File

@ -2,7 +2,7 @@
/*
* Device Tree Source for J721S2 SoC Family
*
* TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
* TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
@ -81,6 +81,7 @@
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
firmware {
@ -163,6 +164,10 @@
};
};
thermal_zones: thermal-zones {
#include "k3-j721s2-thermal.dtsi"
};
};
/* Now include peripherals from each bus segment */

618
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
View File

@ -20,10 +20,13 @@
};
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart8;
mmc0 = &main_sdhci0;
mmc1 = &main_sdhci1;
i2c0 = &main_i2c0;
i2c0 = &wkup_i2c0;
i2c3 = &main_i2c0;
};
memory@80000000 {
@ -42,6 +45,150 @@
reg = <0x00 0x9e800000 0x00 0x01800000>;
no-map;
};
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa5100000 0x00 0xf00000>;
no-map;
};
main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6000000 0x00 0x100000>;
no-map;
};
main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa6100000 0x00 0xf00000>;
no-map;
};
main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7000000 0x00 0x100000>;
no-map;
};
main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa7100000 0x00 0xf00000>;
no-map;
};
c71_0_dma_memory_region: c71-dma-memory@a8000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa8000000 0x00 0x100000>;
no-map;
};
c71_0_memory_region: c71-memory@a8100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa8100000 0x00 0xf00000>;
no-map;
};
c71_1_dma_memory_region: c71-dma-memory@a9000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa9000000 0x00 0x100000>;
no-map;
};
c71_1_memory_region: c71-memory@a9100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa9100000 0x00 0xf00000>;
no-map;
};
c71_2_dma_memory_region: c71-dma-memory@aa000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xaa000000 0x00 0x100000>;
no-map;
};
c71_2_memory_region: c71-memory@aa100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xaa100000 0x00 0xf00000>;
no-map;
};
c71_3_dma_memory_region: c71-dma-memory@ab000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xab000000 0x00 0x100000>;
no-map;
};
c71_3_memory_region: c71-memory@ab100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xab100000 0x00 0xf00000>;
no-map;
};
};
evm_12v0: regulator-evm12v0 {
@ -105,7 +252,7 @@
};
&main_pmx0 {
main_uart8_pins_default: main-uart8-pins-default {
main_uart8_pins_default: main-uart8-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */
@ -114,14 +261,14 @@
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
@ -134,37 +281,147 @@
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
>;
};
};
&wkup_pmx0 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
&wkup_pmx2 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */
J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */
>;
};
mcu_mdio_pins_default: mcu-mdio-pins-default {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
>;
};
mcu_uart0_pins_default: mcu-uart0-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */
J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */
J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
>;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
>;
};
mcu_mdio_pins_default: mcu-mdio-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
>;
};
mcu_adc0_pins_default: mcu-adc0-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */
J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */
J784S4_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */
J784S4_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */
J784S4_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */
J784S4_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */
J784S4_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */
J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */
>;
};
mcu_adc1_pins_default: mcu-adc1-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */
J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */
J784S4_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */
J784S4_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */
J784S4_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */
J784S4_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */
J784S4_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */
J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */
>;
};
};
&wkup_pmx0 {
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */
J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */
J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */
J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */
J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */
J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */
J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */
J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */
J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */
J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */
J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */
J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */
>;
};
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
pinctrl-single,pins = <
J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */
J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */
J784S4_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */
J784S4_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */
J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */
J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */
J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */
J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */
>;
};
};
&wkup_uart0 {
/* Firmware usage */
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&wkup_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
eeprom@50 {
/* CAV24C256WE-GT3 */
compatible = "atmel,24c256";
reg = <0x50>;
};
};
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
};
&main_uart8 {
@ -173,6 +430,131 @@
pinctrl-0 = <&main_uart8_pins_default>;
};
&fss {
status = "okay";
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <25000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "ospi.env.backup";
reg = <0x6c0000 0x40000>;
};
partition@800000 {
label = "ospi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&ospi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
flash@0{
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <40000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
cdns,read-delay = <2>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qspi.tiboot3";
reg = <0x0 0x80000>;
};
partition@80000 {
label = "qspi.tispl";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "qspi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "qspi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "qspi.env.backup";
reg = <0x6c0000 0x40000>;
};
partition@800000 {
label = "qspi.rootfs";
reg = <0x800000 0x37c0000>;
};
partition@3fc0000 {
label = "qspi.phypattern";
reg = <0x3fc0000 0x40000>;
};
};
};
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
@ -253,3 +635,195 @@
phy-mode = "rgmii-rxid";
phy-handle = <&mcu_phy0>;
};
&mailbox0_cluster0 {
status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster1 {
status = "okay";
interrupts = <432>;
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster2 {
status = "okay";
interrupts = <428>;
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster3 {
status = "okay";
interrupts = <424>;
mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster4 {
status = "okay";
interrupts = <420>;
mbox_c71_0: mbox-c71-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c71_1: mbox-c71-1 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mailbox0_cluster5 {
status = "okay";
interrupts = <416>;
mbox_c71_2: mbox-c71-2 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
mbox_c71_3: mbox-c71-3 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&mcu_r5fss0_core0 {
status = "okay";
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
};
&mcu_r5fss0_core1 {
status = "okay";
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
<&mcu_r5fss0_core1_memory_region>;
};
&main_r5fss0_core0 {
status = "okay";
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
status = "okay";
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
status = "okay";
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
status = "okay";
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&main_r5fss2_core0 {
status = "okay";
mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>;
memory-region = <&main_r5fss2_core0_dma_memory_region>,
<&main_r5fss2_core0_memory_region>;
};
&main_r5fss2_core1 {
status = "okay";
mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>;
memory-region = <&main_r5fss2_core1_dma_memory_region>,
<&main_r5fss2_core1_memory_region>;
};
&c71_0 {
status = "okay";
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
&c71_1 {
status = "okay";
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
memory-region = <&c71_1_dma_memory_region>,
<&c71_1_memory_region>;
};
&c71_2 {
status = "okay";
mboxes = <&mailbox0_cluster5 &mbox_c71_2>;
memory-region = <&c71_2_dma_memory_region>,
<&c71_2_memory_region>;
};
&c71_3 {
status = "okay";
mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
memory-region = <&c71_3_dma_memory_region>,
<&c71_3_memory_region>;
};
&tscadc0 {
pinctrl-0 = <&mcu_adc0_pins_default>;
pinctrl-names = "default";
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&tscadc1 {
pinctrl-0 = <&mcu_adc1_pins_default>;
pinctrl-names = "default";
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};

427
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
View File

@ -72,6 +72,24 @@
pinctrl-single,function-mask = <0xffffffff>;
};
/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
main_timerio_input: pinctrl@104200 {
compatible = "pinctrl-single";
reg = <0x00 0x104200 0x00 0x50>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000007>;
};
/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
main_timerio_output: pinctrl@104280 {
compatible = "pinctrl-single";
reg = <0x00 0x104280 0x00 0x20>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000001f>;
};
main_crypto: crypto@4e00000 {
compatible = "ti,j721e-sa2ul";
reg = <0x00 0x4e00000 0x00 0x1200>;
@ -91,6 +109,246 @@
};
};
main_timer0: timer@2400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 97 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 97 2>;
assigned-clock-parents = <&k3_clks 97 3>;
power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer1: timer@2410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2410000 0x00 0x400>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 98 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 98 2>;
assigned-clock-parents = <&k3_clks 98 3>;
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer2: timer@2420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2420000 0x00 0x400>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 99 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 99 2>;
assigned-clock-parents = <&k3_clks 99 3>;
power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer3: timer@2430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2430000 0x00 0x400>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 100 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 100 2>;
assigned-clock-parents = <&k3_clks 100 3>;
power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer4: timer@2440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2440000 0x00 0x400>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 101 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 101 2>;
assigned-clock-parents = <&k3_clks 101 3>;
power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer5: timer@2450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2450000 0x00 0x400>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 102 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 102 2>;
assigned-clock-parents = <&k3_clks 102 3>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer6: timer@2460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2460000 0x00 0x400>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 103 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 103 2>;
assigned-clock-parents = <&k3_clks 103 3>;
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer7: timer@2470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2470000 0x00 0x400>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 104 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 104 2>;
assigned-clock-parents = <&k3_clks 104 3>;
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer8: timer@2480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2480000 0x00 0x400>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 105 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 105 2>;
assigned-clock-parents = <&k3_clks 105 3>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer9: timer@2490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2490000 0x00 0x400>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 106 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 106 2>;
assigned-clock-parents = <&k3_clks 106 3>;
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer10: timer@24a0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24a0000 0x00 0x400>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 107 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 107 2>;
assigned-clock-parents = <&k3_clks 107 3>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer11: timer@24b0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24b0000 0x00 0x400>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 108 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 108 2>;
assigned-clock-parents = <&k3_clks 108 3>;
power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer12: timer@24c0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24c0000 0x00 0x400>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 109 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 109 2>;
assigned-clock-parents = <&k3_clks 109 3>;
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer13: timer@24d0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24d0000 0x00 0x400>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 110 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 110 2>;
assigned-clock-parents = <&k3_clks 110 3>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer14: timer@24e0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24e0000 0x00 0x400>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 111 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 111 2>;
assigned-clock-parents = <&k3_clks 111 3>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer15: timer@24f0000 {
compatible = "ti,am654-timer";
reg = <0x00 0x24f0000 0x00 0x400>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 112 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 112 2>;
assigned-clock-parents = <&k3_clks 112 3>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer16: timer@2500000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2500000 0x00 0x400>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 113 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 113 2>;
assigned-clock-parents = <&k3_clks 113 3>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer17: timer@2510000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2510000 0x00 0x400>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 114 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 114 2>;
assigned-clock-parents = <&k3_clks 114 3>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer18: timer@2520000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2520000 0x00 0x400>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 115 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 115 2>;
assigned-clock-parents = <&k3_clks 115 3>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_timer19: timer@2530000 {
compatible = "ti,am654-timer";
reg = <0x00 0x2530000 0x00 0x400>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 116 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 116 2>;
assigned-clock-parents = <&k3_clks 116 3>;
power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
@ -378,7 +636,6 @@
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
no-1-8-v;
status = "disabled";
};
@ -1112,4 +1369,172 @@
clocks = <&k3_clks 383 1>;
status = "disabled";
};
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
<0x5d00000 0x00 0x5d00000 0x20000>;
power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
main_r5fss0_core0: r5f@5c00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5c00000 0x00010000>,
<0x5c10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <339>;
ti,sci-proc-ids = <0x06 0xff>;
resets = <&k3_reset 339 1>;
firmware-name = "j784s4-main-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss0_core1: r5f@5d00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5d00000 0x00010000>,
<0x5d10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <340>;
ti,sci-proc-ids = <0x07 0xff>;
resets = <&k3_reset 340 1>;
firmware-name = "j784s4-main-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
main_r5fss1: r5fss@5e00000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
<0x5f00000 0x00 0x5f00000 0x20000>;
power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>;
main_r5fss1_core0: r5f@5e00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5e00000 0x00010000>,
<0x5e10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <341>;
ti,sci-proc-ids = <0x08 0xff>;
resets = <&k3_reset 341 1>;
firmware-name = "j784s4-main-r5f1_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss1_core1: r5f@5f00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5f00000 0x00010000>,
<0x5f10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <342>;
ti,sci-proc-ids = <0x09 0xff>;
resets = <&k3_reset 342 1>;
firmware-name = "j784s4-main-r5f1_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
main_r5fss2: r5fss@5900000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x5900000 0x00 0x5900000 0x20000>,
<0x5a00000 0x00 0x5a00000 0x20000>;
power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>;
main_r5fss2_core0: r5f@5900000 {
compatible = "ti,j721s2-r5f";
reg = <0x5900000 0x00010000>,
<0x5910000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <343>;
ti,sci-proc-ids = <0x0a 0xff>;
resets = <&k3_reset 343 1>;
firmware-name = "j784s4-main-r5f2_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
main_r5fss2_core1: r5f@5a00000 {
compatible = "ti,j721s2-r5f";
reg = <0x5a00000 0x00010000>,
<0x5a10000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <344>;
ti,sci-proc-ids = <0x0b 0xff>;
resets = <&k3_reset 344 1>;
firmware-name = "j784s4-main-r5f2_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
c71_0: dsp@64800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x64800000 0x00 0x00080000>,
<0x00 0x64e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <30>;
ti,sci-proc-ids = <0x30 0xff>;
resets = <&k3_reset 30 1>;
firmware-name = "j784s4-c71_0-fw";
};
c71_1: dsp@65800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x65800000 0x00 0x00080000>,
<0x00 0x65e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <33>;
ti,sci-proc-ids = <0x31 0xff>;
resets = <&k3_reset 33 1>;
firmware-name = "j784s4-c71_1-fw";
};
c71_2: dsp@66800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x66800000 0x00 0x00080000>,
<0x00 0x66e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <37>;
ti,sci-proc-ids = <0x32 0xff>;
resets = <&k3_reset 37 1>;
firmware-name = "j784s4-c71_2-fw";
};
c71_3: dsp@67800000 {
compatible = "ti,j721s2-c71-dsp";
reg = <0x00 0x67800000 0x00 0x00080000>,
<0x00 0x67e00000 0x00 0x0000c000>;
reg-names = "l2sram", "l1dram";
ti,sci = <&sms>;
ti,sci-dev-id = <40>;
ti,sci-proc-ids = <0x33 0xff>;
resets = <&k3_reset 40 1>;
firmware-name = "j784s4-c71_3-fw";
};
};

350
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
View File

@ -39,6 +39,21 @@
reg = <0x00 0x43000014 0x00 0x4>;
};
secure_proxy_sa3: mailbox@43600000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x43600000 0x00 0x10000>,
<0x00 0x44880000 0x00 0x20000>,
<0x00 0x44860000 0x00 0x20000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
mcu_ram: sram@41c00000 {
compatible = "mmio-sram";
reg = <0x00 0x41c00000 0x00 0x100000>;
@ -50,7 +65,34 @@
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x178>;
reg = <0x00 0x4301c000 0x00 0x034>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx1: pinctrl@4301c038 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c038 0x00 0x02c>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx2: pinctrl@4301c068 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c068 0x00 0x120>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_pmx3: pinctrl@4301c190 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c190 0x00 0x004>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
@ -68,6 +110,28 @@
ti,interrupt-ranges = <16 928 16>;
};
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
mcu_timerio_input: pinctrl@40f04200 {
compatible = "pinctrl-single";
reg = <0x00 0x40f04200 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Non-MPU Firmware usage */
status = "reserved";
};
/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
mcu_timerio_output: pinctrl@40f04280 {
compatible = "pinctrl-single";
reg = <0x00 0x40f04280 0x00 0x28>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_conf: syscon@40f00000 {
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
reg = <0x00 0x40f00000 0x00 0x20000>;
@ -82,6 +146,146 @@
};
};
mcu_timer0: timer@40400000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40400000 0x00 0x400>;
interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 35 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 35 2>;
assigned-clock-parents = <&k3_clks 35 3>;
power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer1: timer@40410000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40410000 0x00 0x400>;
interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 117 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 117 2>;
assigned-clock-parents = <&k3_clks 117 3>;
power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer2: timer@40420000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40420000 0x00 0x400>;
interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 118 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 118 2>;
assigned-clock-parents = <&k3_clks 118 3>;
power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer3: timer@40430000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40430000 0x00 0x400>;
interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 119 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 119 2>;
assigned-clock-parents = <&k3_clks 119 3>;
power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer4: timer@40440000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40440000 0x00 0x400>;
interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 120 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 120 2>;
assigned-clock-parents = <&k3_clks 120 3>;
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer5: timer@40450000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40450000 0x00 0x400>;
interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 121 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 121 2>;
assigned-clock-parents = <&k3_clks 121 3>;
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer6: timer@40460000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40460000 0x00 0x400>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 122 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 122 2>;
assigned-clock-parents = <&k3_clks 122 3>;
power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer7: timer@40470000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40470000 0x00 0x400>;
interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 123 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 123 2>;
assigned-clock-parents = <&k3_clks 123 3>;
power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer8: timer@40480000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40480000 0x00 0x400>;
interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 124 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 124 2>;
assigned-clock-parents = <&k3_clks 124 3>;
power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
mcu_timer9: timer@40490000 {
compatible = "ti,am654-timer";
reg = <0x00 0x40490000 0x00 0x400>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 125 2>;
clock-names = "fck";
assigned-clocks = <&k3_clks 125 2>;
assigned-clock-parents = <&k3_clks 125 3>;
power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
ti,timer-pwm;
/* Non-MPU Firmware usage */
status = "reserved";
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x200>;
@ -280,6 +484,21 @@
};
};
secure_proxy_mcu: mailbox@2a480000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x2a480000 0x00 0x80000>,
<0x00 0x2a380000 0x00 0x80000>,
<0x00 0x2a400000 0x00 0x80000>;
/*
* Marked Disabled:
* Node is incomplete as it is meant for bootloaders and
* firmware on non-MPU processors
*/
status = "disabled";
};
mcu_cpsw: ethernet@46000000 {
compatible = "ti,j721e-cpsw-nuss";
#address-cells = <2>;
@ -342,4 +561,133 @@
ti,cpts-periodic-outputs = <2>;
};
};
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j721s2-r5fss";
ti,cluster-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
mcu_r5fss0_core0: r5f@41000000 {
compatible = "ti,j721s2-r5f";
reg = <0x41000000 0x00010000>,
<0x41010000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <346>;
ti,sci-proc-ids = <0x01 0xff>;
resets = <&k3_reset 346 1>;
firmware-name = "j784s4-mcu-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
compatible = "ti,j721s2-r5f";
reg = <0x41400000 0x00010000>,
<0x41410000 0x00010000>;
reg-names = "atcm", "btcm";
ti,sci = <&sms>;
ti,sci-dev-id = <347>;
ti,sci-proc-ids = <0x02 0xff>;
resets = <&k3_reset 347 1>;
firmware-name = "j784s4-mcu-r5f0_1-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
wkup_vtm0: temperature-sensor@42040000 {
compatible = "ti,j7200-vtm";
reg = <0x00 0x42040000 0x00 0x350>,
<0x00 0x42050000 0x00 0x350>;
power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
tscadc0: tscadc@40200000 {
compatible = "ti,am3359-tscadc";
reg = <0x00 0x40200000 0x00 0x1000>;
interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 0 0>;
assigned-clocks = <&k3_clks 0 2>;
assigned-clock-rates = <60000000>;
clock-names = "fck";
dmas = <&main_udmap 0x7400>,
<&main_udmap 0x7401>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
tscadc1: tscadc@40210000 {
compatible = "ti,am3359-tscadc";
reg = <0x00 0x40210000 0x00 0x1000>;
interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 1 0>;
assigned-clocks = <&k3_clks 1 2>;
assigned-clock-rates = <60000000>;
clock-names = "fck";
dmas = <&main_udmap 0x7402>,
<&main_udmap 0x7403>;
dma-names = "fifo0", "fifo1";
status = "disabled";
adc {
#io-channel-cells = <1>;
compatible = "ti,am3359-adc";
};
};
fss: bus@47000000 {
compatible = "simple-bus";
reg = <0x00 0x47000000 0x00 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47040000 0x00 0x100>,
<0x05 0x0000000 0x01 0x0000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 161 7>;
assigned-clocks = <&k3_clks 161 7>;
assigned-clock-parents = <&k3_clks 161 9>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ospi1: spi@47050000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x47050000 0x00 0x100>,
<0x07 0x0000000 0x01 0x0000000>;
interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 162 7>;
power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};

101
arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi Normal file
View File

@ -0,0 +1,101 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/thermal/thermal.h>
wkup0_thermal: wkup0-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 0>;
trips {
wkup0_crit: wkup0-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
wkup1_thermal: wkup1-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 1>;
trips {
wkup1_crit: wkup1-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main0_thermal: main0-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 2>;
trips {
main0_crit: main0-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main1_thermal: main1-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 3>;
trips {
main1_crit: main1-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main2_thermal: main2-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 4>;
trips {
main2_crit: main2-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main3_thermal: main3-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 5>;
trips {
main3_crit: main3-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};
main4_thermal: main4-thermal {
polling-delay-passive = <250>; /* milliseconds */
polling-delay = <500>; /* milliseconds */
thermal-sensors = <&wkup_vtm0 6>;
trips {
main4_crit: main4-crit {
temperature = <125000>; /* milliCelsius */
hysteresis = <2000>; /* milliCelsius */
type = "critical";
};
};
};

6
arch/arm64/boot/dts/ti/k3-j784s4.dtsi
View File

@ -2,7 +2,7 @@
/*
* Device Tree Source for J784S4 SoC Family
*
* TRM (SPRUJ43 JULY 2022) : http://www.ti.com/lit/zip/spruj52
* TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*
@ -281,6 +281,10 @@
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
};
};
thermal_zones: thermal-zones {
#include "k3-j784s4-thermal.dtsi"
};
};
/* Now include peripherals from each bus segment */