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cpufreq: imx-cpufreq-dt: Correct i.MX8MN's default speed grade value

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i.MX8MN has different speed grade definition compared to
i.MX8MQ/i.MX8MM, when fuses are NOT written, the default
speed_grade should be set to minimum available OPP defined
in DT which is 1.2GHz, the corresponding speed_grade value
should be 0xb.

Fixes: 5b8010ba70d5 ("cpufreq: imx-cpufreq-dt: Add i.MX8MN support")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Anson Huang 2019-10-22 16:33:19 +08:00 committed by Viresh Kumar
parent e318d2c8f3
commit af44d180e3
1 changed files with 10 additions and 10 deletions
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20
drivers/cpufreq/imx-cpufreq-dt.c
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@ -44,19 +44,19 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT; mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
/* /*
* Early samples without fuses written report "0 0" which means * Early samples without fuses written report "0 0" which may NOT
* consumer segment and minimum speed grading. * match any OPP defined in DT. So clamp to minimum OPP defined in
* * DT to avoid warning for "no OPPs".
* According to datasheet minimum speed grading is not supported for
* consumer parts so clamp to 1 to avoid warning for "no OPPs"
* *
* Applies to i.MX8M series SoCs. * Applies to i.MX8M series SoCs.
*/ */
if (mkt_segment == 0 && speed_grade == 0 && ( if (mkt_segment == 0 && speed_grade == 0) {
of_machine_is_compatible("fsl,imx8mm") || if (of_machine_is_compatible("fsl,imx8mm") ||
of_machine_is_compatible("fsl,imx8mn") || of_machine_is_compatible("fsl,imx8mq"))
of_machine_is_compatible("fsl,imx8mq"))) speed_grade = 1;
speed_grade = 1; if (of_machine_is_compatible("fsl,imx8mn"))
speed_grade = 0xb;
}
supported_hw[0] = BIT(speed_grade); supported_hw[0] = BIT(speed_grade);
supported_hw[1] = BIT(mkt_segment); supported_hw[1] = BIT(mkt_segment);