net: pcs: Add 10GBASE-R mode for Synopsys Designware XPCS
Add basic support for XPCS using 10GBASE-R interface. This mode will be extended to use interrupt, so set pcs.poll false. And avoid soft reset so that the device using this mode is in the default configuration. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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@ -64,6 +64,16 @@ static const int xpcs_xlgmii_features[] = {
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__ETHTOOL_LINK_MODE_MASK_NBITS,
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};
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static const int xpcs_10gbaser_features[] = {
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ETHTOOL_LINK_MODE_Pause_BIT,
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ETHTOOL_LINK_MODE_Asym_Pause_BIT,
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ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
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ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
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ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
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ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
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__ETHTOOL_LINK_MODE_MASK_NBITS,
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};
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static const int xpcs_sgmii_features[] = {
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ETHTOOL_LINK_MODE_Pause_BIT,
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ETHTOOL_LINK_MODE_Asym_Pause_BIT,
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@ -106,6 +116,10 @@ static const phy_interface_t xpcs_xlgmii_interfaces[] = {
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PHY_INTERFACE_MODE_XLGMII,
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};
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static const phy_interface_t xpcs_10gbaser_interfaces[] = {
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PHY_INTERFACE_MODE_10GBASER,
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};
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static const phy_interface_t xpcs_sgmii_interfaces[] = {
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PHY_INTERFACE_MODE_SGMII,
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};
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@ -123,6 +137,7 @@ enum {
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DW_XPCS_USXGMII,
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DW_XPCS_10GKR,
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DW_XPCS_XLGMII,
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DW_XPCS_10GBASER,
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DW_XPCS_SGMII,
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DW_XPCS_1000BASEX,
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DW_XPCS_2500BASEX,
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@ -246,6 +261,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs,
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switch (compat->an_mode) {
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case DW_AN_C73:
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case DW_10GBASER:
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dev = MDIO_MMD_PCS;
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break;
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case DW_AN_C37_SGMII:
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@ -802,6 +818,8 @@ int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
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return -ENODEV;
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switch (compat->an_mode) {
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case DW_10GBASER:
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break;
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case DW_AN_C73:
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if (test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) {
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ret = xpcs_config_aneg_c73(xpcs, compat);
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@ -998,6 +1016,9 @@ static void xpcs_get_state(struct phylink_pcs *pcs,
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return;
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switch (compat->an_mode) {
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case DW_10GBASER:
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phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state);
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break;
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case DW_AN_C73:
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ret = xpcs_get_state_c73(xpcs, state, compat);
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if (ret) {
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@ -1153,6 +1174,12 @@ static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
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.num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
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.an_mode = DW_AN_C73,
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},
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[DW_XPCS_10GBASER] = {
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.supported = xpcs_10gbaser_features,
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.interface = xpcs_10gbaser_interfaces,
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.num_interfaces = ARRAY_SIZE(xpcs_10gbaser_interfaces),
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.an_mode = DW_10GBASER,
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},
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[DW_XPCS_SGMII] = {
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.supported = xpcs_sgmii_features,
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.interface = xpcs_sgmii_interfaces,
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@ -1256,6 +1283,9 @@ static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
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}
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xpcs->pcs.ops = &xpcs_phylink_ops;
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if (compat->an_mode == DW_10GBASER)
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return xpcs;
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xpcs->pcs.poll = true;
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ret = xpcs_soft_reset(xpcs, compat);
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@ -18,6 +18,7 @@
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#define DW_AN_C37_SGMII 2
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#define DW_2500BASEX 3
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#define DW_AN_C37_1000BASEX 4
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#define DW_10GBASER 5
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struct xpcs_id;
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