drm/nouveau/tmr: fix miscalculation of ratio on pre-nv4x chipsets
The clock_get() hook returns KHz, not Hz. Also fixed to use crystal freq from dev_priv. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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parent
378f85ed54
commit
afb0c796d8
@ -3,30 +3,6 @@
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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static u32
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nv04_crystal_freq(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 extdev_boot0 = nv_rd32(dev, 0x101000);
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int type;
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type = !!(extdev_boot0 & 0x00000040);
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if ((dev_priv->chipset >= 0x17 && dev_priv->chipset < 0x20) ||
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dev_priv->chipset >= 0x25)
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type |= (extdev_boot0 & 0x00400000) ? 2 : 0;
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switch (type) {
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case 0: return 13500000;
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case 1: return 14318180;
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case 2: return 27000000;
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case 3: return 25000000;
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default:
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break;
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}
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return 0;
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}
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int
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nv04_timer_init(struct drm_device *dev)
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{
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@ -37,7 +13,7 @@ nv04_timer_init(struct drm_device *dev)
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nv_wr32(dev, NV04_PTIMER_INTR_0, 0xFFFFFFFF);
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/* aim for 31.25MHz, which gives us nanosecond timestamps */
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d = 1000000000 / 32;
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d = 1000000 / 32;
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/* determine base clock for timer source */
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if (dev_priv->chipset < 0x40) {
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@ -47,7 +23,7 @@ nv04_timer_init(struct drm_device *dev)
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/*XXX: figure this out */
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n = 0;
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} else {
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n = nv04_crystal_freq(dev);
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n = dev_priv->crystal;
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m = 1;
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while (n < (d * 2)) {
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n += (n / m);
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