ASoC: SOF: Intel: hda: add SSP info to the chip info struct
add SSP info of APL and CNL, to the sof_intel_dsp_desc structure. The max SSP count the platform support and the SSP base address. Signed-off-by: Zhu Yingjiang <yingjiang.zhu@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -105,5 +105,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
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.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
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.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
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.ipc_ctl = HDA_DSP_REG_HIPCCTL,
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.ipc_ctl = HDA_DSP_REG_HIPCCTL,
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.rom_init_timeout = 150,
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.rom_init_timeout = 150,
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.ssp_count = APL_SSP_COUNT,
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.ssp_base_offset = APL_SSP_BASE_OFFSET,
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};
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};
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EXPORT_SYMBOL(apl_chip_info);
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EXPORT_SYMBOL(apl_chip_info);
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@ -246,5 +246,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_init_timeout = 300,
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.rom_init_timeout = 300,
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.ssp_count = CNL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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};
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};
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EXPORT_SYMBOL(cnl_chip_info);
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EXPORT_SYMBOL(cnl_chip_info);
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@ -345,6 +345,10 @@
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/* Host Device Memory Size of a Single SSP */
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/* Host Device Memory Size of a Single SSP */
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#define SSP_DEV_MEM_SIZE 0x1000
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#define SSP_DEV_MEM_SIZE 0x1000
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/* SSP Count of the Platform */
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#define APL_SSP_COUNT 6
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#define CNL_SSP_COUNT 3
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#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
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#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
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struct sof_intel_dsp_bdl {
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struct sof_intel_dsp_bdl {
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@ -162,6 +162,8 @@ struct sof_intel_dsp_desc {
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int ipc_ack_mask;
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int ipc_ack_mask;
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int ipc_ctl;
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int ipc_ctl;
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int rom_init_timeout;
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int rom_init_timeout;
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int ssp_count; /* ssp count of the platform */
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int ssp_base_offset; /* base address of the SSPs */
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};
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};
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extern const struct snd_sof_dsp_ops sof_tng_ops;
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extern const struct snd_sof_dsp_ops sof_tng_ops;
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