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drm/amd/display: Add support for visual confirm color

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[Why]
We want to get the visual confirm color of the bottom-most pipe
for test automation.

[How]
Save the visual confirm color to plane_state before program to MPC;

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo (Hanghong) Ma 2022-07-29 11:46:13 -04:00 committed by Alex Deucher
parent 36527db318
commit b09c1fff5a
7 changed files with 84 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -1183,6 +1183,7 @@ struct dc_plane_state {
/* private to dc_surface.c */
enum dc_irq_source irq_source;
struct kref refcount;
struct tg_color visual_confirm_color;
};
struct dc_plane_info {

31
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
View File

@ -389,6 +389,37 @@ void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub)
}
}
void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
union dmub_rb_cmd cmd = { 0 };
enum dmub_status status;
unsigned int panel_inst = 0;
dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst);
memset(&cmd, 0, sizeof(cmd));
// Prepare fw command
cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR;
cmd.visual_confirm_color.header.sub_type = 0;
cmd.visual_confirm_color.header.ret_status = 1;
cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
// Send command to fw
status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, &cmd);
ASSERT(status == DMUB_STATUS_OK);
// If command was processed, copy feature caps to dmub srv
if (status == DMUB_STATUS_OK &&
cmd.visual_confirm_color.header.ret_status == 0) {
memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,
&cmd.visual_confirm_color.visual_confirm_color_data,
sizeof(struct dmub_visual_confirm_color));
}
}
#ifdef CONFIG_DRM_AMD_DC_DCN
/**
* ***********************************************************************************************

1
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
View File

@ -78,6 +78,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst);
bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool enable_pstate, struct dc_state *context);
void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub);
void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx);
void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);
void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -2539,8 +2539,10 @@ void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx,
color_space_to_black_color(
dc, pipe_ctx->stream->output_color_space, color);
if (mpc->funcs->set_bg_color)
if (mpc->funcs->set_bg_color) {
memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
}
}
void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -2466,8 +2466,10 @@ void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx,
else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
get_surface_tile_visual_confirm_color(pipe_ctx, color);
if (mpc->funcs->set_bg_color)
if (mpc->funcs->set_bg_color) {
memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color));
mpc->funcs->set_bg_color(mpc, color, mpcc_id);
}
}
void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)

1
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
View File

@ -441,6 +441,7 @@ struct dmub_srv {
/* Feature capabilities reported by fw */
struct dmub_feature_caps feature_caps;
struct dmub_visual_confirm_color visual_confirm_color;
};
/**

44
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
View File

@ -246,6 +246,16 @@ struct dmub_feature_caps {
uint8_t reserved[6];
};
struct dmub_visual_confirm_color {
/**
* Maximum 10 bits color value
*/
uint16_t color_r_cr;
uint16_t color_g_y;
uint16_t color_b_cb;
uint16_t panel_inst;
};
#if defined(__cplusplus)
}
#endif
@ -644,6 +654,10 @@ enum dmub_cmd_type {
* Command type used to query FW feature caps.
*/
DMUB_CMD__QUERY_FEATURE_CAPS = 6,
/**
* Command type used to get visual confirm color.
*/
DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
/**
* Command type used for all PSR commands.
*/
@ -2778,6 +2792,31 @@ struct dmub_rb_cmd_query_feature_caps {
struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
};
/**
* Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
*/
struct dmub_cmd_visual_confirm_color_data {
/**
* DMUB feature capabilities.
* After DMUB init, driver will query FW capabilities prior to enabling certain features.
*/
struct dmub_visual_confirm_color visual_confirm_color;
};
/**
* Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
*/
struct dmub_rb_cmd_get_visual_confirm_color {
/**
* Command header.
*/
struct dmub_cmd_header header;
/**
* Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
*/
struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
};
struct dmub_optc_state {
uint32_t v_total_max;
uint32_t v_total_min;
@ -3150,6 +3189,11 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
*/
struct dmub_rb_cmd_query_feature_caps query_feature_caps;
/**
* Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
*/
struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
struct dmub_rb_cmd_drr_update drr_update;
struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;