arm64: cpufeature: detect FEAT_HCX
Detect if the system has the new HCRX_EL2 register added in ARMv8.7/9.2, so that subsequent patches can check for its presence. KVM currently relies on the register being present on all CPUs (or none), so the kernel will panic if that is not the case. Fortunately no such systems currently exist, but this can be revisited if they appear. Note that the kernel will not panic if CONFIG_KVM is disabled. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com> Link: https://lore.kernel.org/r/20230509142235.3284028-3-kristina.martsenko@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -364,6 +364,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
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static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
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@ -2309,6 +2310,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = is_kvm_protected_mode,
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},
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{
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.desc = "HCRX_EL2 register",
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.capability = ARM64_HAS_HCX,
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.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
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.matches = has_cpuid_feature,
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ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP)
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},
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#endif
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{
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.desc = "Kernel page table isolation (KPTI)",
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@ -32,6 +32,7 @@ HAS_GENERIC_AUTH_IMP_DEF
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HAS_GIC_CPUIF_SYSREGS
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HAS_GIC_PRIO_MASKING
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HAS_GIC_PRIO_RELAXED_SYNC
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HAS_HCX
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HAS_LDAPR
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HAS_LSE_ATOMICS
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HAS_NESTED_VIRT
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