ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables
This pinmux tables currently omit any configuration for PCIe clk_req, wake, and rst pins, which in turn causes intermittent failures in U-Boot's PCIe support. Import an updated version of the pinmux tables which rectifies this. (While I'm still hoping to remove the pinmux tables from DTs for Tegra124+ devices, while they're still here, they may as well be complete and correct). Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
@@ -1231,6 +1231,41 @@
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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};
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pex_l0_rst_n_pdd1 {
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nvidia,pins = "pex_l0_rst_n_pdd1";
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nvidia,function = "pe0";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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pex_l0_clkreq_n_pdd2 {
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nvidia,pins = "pex_l0_clkreq_n_pdd2";
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nvidia,function = "pe0";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pex_wake_n_pdd3 {
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nvidia,pins = "pex_wake_n_pdd3";
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nvidia,function = "pe";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pex_l1_rst_n_pdd5 {
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nvidia,pins = "pex_l1_rst_n_pdd5";
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nvidia,function = "pe1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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pex_l1_clkreq_n_pdd6 {
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nvidia,pins = "pex_l1_clkreq_n_pdd6";
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nvidia,function = "pe1";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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clk3_out_pee0 {
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clk3_out_pee0 {
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nvidia,pins = "clk3_out_pee0";
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nvidia,pins = "clk3_out_pee0";
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nvidia,function = "extperiph3";
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nvidia,function = "extperiph3";
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