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Merge branches 'apple/dart', 'arm/mediatek', 'arm/msm', 'arm/smmu', 'ppc/pamu', 'x86/vt-d', 'x86/amd' and 'vfio-notifier-fix' into next

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This commit is contained in:
Joerg Roedel 2022-05-20 12:27:17 +02:00
commit b0dacee202
787 changed files with 9052 additions and 4706 deletions
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3
.mailmap
View File

@ -45,6 +45,7 @@ Andrey Konovalov <andreyknvl@gmail.com> <andreyknvl@google.com>
Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
Andrey Ryabinin <ryabinin.a.a@gmail.com> <aryabinin@virtuozzo.com>
Andrzej Hajda <andrzej.hajda@intel.com> <a.hajda@samsung.com>
André Almeida <andrealmeid@igalia.com> <andrealmeid@collabora.com>
Andy Adamson <andros@citi.umich.edu>
Antoine Tenart <atenart@kernel.org> <antoine.tenart@bootlin.com>
Antoine Tenart <atenart@kernel.org> <antoine.tenart@free-electrons.com>
@ -204,6 +205,7 @@ Juha Yrjola <at solidboot.com>
Juha Yrjola <juha.yrjola@nokia.com>
Juha Yrjola <juha.yrjola@solidboot.com>
Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com>
Kalle Valo <kvalo@kernel.org> <kvalo@codeaurora.org>
Kalyan Thota <quic_kalyant@quicinc.com> <kalyan_t@codeaurora.org>
Kay Sievers <kay.sievers@vrfy.org>
Kees Cook <keescook@chromium.org> <kees.cook@canonical.com>
@ -249,6 +251,7 @@ Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com>
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
Martyna Szapar-Mudlaw <martyna.szapar-mudlaw@linux.intel.com> <martyna.szapar-mudlaw@intel.com>
Mathieu Othacehe <m.othacehe@gmail.com>
Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>
Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>

4
Documentation/arm64/memory-tagging-extension.rst
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@ -228,10 +228,10 @@ Core dump support
-----------------
The allocation tags for user memory mapped with ``PROT_MTE`` are dumped
in the core file as additional ``PT_ARM_MEMTAG_MTE`` segments. The
in the core file as additional ``PT_AARCH64_MEMTAG_MTE`` segments. The
program header for such segment is defined as:
:``p_type``: ``PT_ARM_MEMTAG_MTE``
:``p_type``: ``PT_AARCH64_MEMTAG_MTE``
:``p_flags``: 0
:``p_offset``: segment file offset
:``p_vaddr``: segment virtual address, same as the corresponding

3
Documentation/arm64/silicon-errata.rst
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@ -189,6 +189,9 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 |
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 |
+----------------+-----------------+-----------------+-----------------------------+
+----------------+-----------------+-----------------+-----------------------------+
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+----------------+-----------------+-----------------+-----------------------------+

4
Documentation/devicetree/bindings/clock/imx8m-clock.yaml
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@ -55,8 +55,6 @@ allOf:
then:
properties:
clocks:
minItems: 7
maxItems: 7
items:
- description: 32k osc
- description: 25m osc
@ -66,8 +64,6 @@ allOf:
- description: ext3 clock input
- description: ext4 clock input
clock-names:
minItems: 7
maxItems: 7
items:
- const: ckil
- const: osc_25m

13
Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
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@ -22,7 +22,16 @@ properties:
const: microchip,mpfs-clkcfg
reg:
maxItems: 1
items:
- description: |
clock config registers:
These registers contain enable, reset & divider tables for the, cpu,
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
for the peripheral clocks.
- description: |
mss pll dri registers:
Block of registers responsible for dynamic reconfiguration of the mss
pll
clocks:
maxItems: 1
@ -51,7 +60,7 @@ examples:
#size-cells = <2>;
clkcfg: clock-controller@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
clocks = <&ref>;
#clock-cells = <1>;
};

4
Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
View File

@ -95,7 +95,6 @@ then:
properties:
clocks:
minItems: 1
maxItems: 4
items:
- description: Functional clock
- description: EXTAL input clock
@ -104,7 +103,6 @@ then:
clock-names:
minItems: 1
maxItems: 4
items:
- const: fck
# The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
@ -128,12 +126,10 @@ then:
else:
properties:
clocks:
maxItems: 1
items:
- description: Functional clock
clock-names:
maxItems: 1
items:
- const: fck

23
Documentation/devicetree/bindings/display/renesas,du.yaml
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@ -109,7 +109,6 @@ allOf:
properties:
clocks:
minItems: 1
maxItems: 3
items:
- description: Functional clock
- description: DU_DOTCLKIN0 input clock
@ -117,7 +116,6 @@ allOf:
clock-names:
minItems: 1
maxItems: 3
items:
- const: du.0
- pattern: '^dclkin\.[01]$'
@ -159,7 +157,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
@ -168,7 +165,6 @@ allOf:
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
@ -216,7 +212,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
@ -225,7 +220,6 @@ allOf:
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
@ -271,7 +265,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
@ -280,7 +273,6 @@ allOf:
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
@ -327,7 +319,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
@ -336,7 +327,6 @@ allOf:
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
@ -386,7 +376,6 @@ allOf:
properties:
clocks:
minItems: 3
maxItems: 6
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
@ -397,7 +386,6 @@ allOf:
clock-names:
minItems: 3
maxItems: 6
items:
- const: du.0
- const: du.1
@ -448,7 +436,6 @@ allOf:
properties:
clocks:
minItems: 4
maxItems: 8
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
@ -461,7 +448,6 @@ allOf:
clock-names:
minItems: 4
maxItems: 8
items:
- const: du.0
- const: du.1
@ -525,7 +511,6 @@ allOf:
properties:
clocks:
minItems: 3
maxItems: 6
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
@ -536,7 +521,6 @@ allOf:
clock-names:
minItems: 3
maxItems: 6
items:
- const: du.0
- const: du.1
@ -596,7 +580,6 @@ allOf:
properties:
clocks:
minItems: 3
maxItems: 6
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
@ -607,7 +590,6 @@ allOf:
clock-names:
minItems: 3
maxItems: 6
items:
- const: du.0
- const: du.1
@ -666,14 +648,12 @@ allOf:
properties:
clocks:
minItems: 1
maxItems: 2
items:
- description: Functional clock for DU0
- description: DU_DOTCLKIN0 input clock
clock-names:
minItems: 1
maxItems: 2
items:
- const: du.0
- const: dclkin.0
@ -723,7 +703,6 @@ allOf:
properties:
clocks:
minItems: 2
maxItems: 4
items:
- description: Functional clock for DU0
- description: Functional clock for DU1
@ -732,7 +711,6 @@ allOf:
clock-names:
minItems: 2
maxItems: 4
items:
- const: du.0
- const: du.1
@ -791,7 +769,6 @@ allOf:
- description: Functional clock
clock-names:
maxItems: 1
items:
- const: du.0

7
Documentation/devicetree/bindings/hwmon/ti,tmp421.yaml
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@ -58,10 +58,9 @@ patternProperties:
description: |
The value (two's complement) to be programmed in the channel specific N correction register.
For remote channels only.
$ref: /schemas/types.yaml#/definitions/uint32
items:
minimum: 0
maximum: 255
$ref: /schemas/types.yaml#/definitions/int32
minimum: -128
maximum: 127
required:
- reg

2
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
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@ -138,7 +138,6 @@ allOf:
- const: bus
- const: adc
minItems: 1
maxItems: 2
interrupts:
items:
@ -170,7 +169,6 @@ allOf:
- const: bus
- const: adc
minItems: 1
maxItems: 2
interrupts:
items:

25
Documentation/devicetree/bindings/iommu/arm,smmu.yaml
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@ -37,8 +37,10 @@ properties:
- qcom,sc7180-smmu-500
- qcom,sc7280-smmu-500
- qcom,sc8180x-smmu-500
- qcom,sc8280xp-smmu-500
- qcom,sdm845-smmu-500
- qcom,sdx55-smmu-500
- qcom,sdx65-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
@ -62,8 +64,9 @@ properties:
for improved performance.
items:
- enum:
- nvidia,tegra194-smmu
- nvidia,tegra186-smmu
- nvidia,tegra194-smmu
- nvidia,tegra234-smmu
- const: nvidia,smmu-500
- items:
- const: arm,mmu-500
@ -157,6 +160,17 @@ properties:
power-domains:
maxItems: 1
nvidia,memory-controller:
description: |
A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
The memory controller needs to be programmed with a mapping of memory
client IDs to ARM SMMU stream IDs.
If this property is absent, the mapping programmed by early firmware
will be used and it is not guaranteed that IOMMU translations will be
enabled for any given device.
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- reg
@ -172,13 +186,20 @@ allOf:
compatible:
contains:
enum:
- nvidia,tegra194-smmu
- nvidia,tegra186-smmu
- nvidia,tegra194-smmu
- nvidia,tegra234-smmu
then:
properties:
reg:
minItems: 1
maxItems: 2
# The reference to the memory controller is required to ensure that the
# memory client to stream ID mapping can be done synchronously with the
# IOMMU attachment.
required:
- nvidia,memory-controller
else:
properties:
reg:

34
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
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@ -76,7 +76,11 @@ properties:
- mediatek,mt8167-m4u # generation two
- mediatek,mt8173-m4u # generation two
- mediatek,mt8183-m4u # generation two
- mediatek,mt8186-iommu-mm # generation two
- mediatek,mt8192-m4u # generation two
- mediatek,mt8195-iommu-vdo # generation two
- mediatek,mt8195-iommu-vpp # generation two
- mediatek,mt8195-iommu-infra # generation two
- description: mt7623 generation one
items:
@ -119,7 +123,9 @@ properties:
dt-binding/memory/mt8167-larb-port.h for mt8167,
dt-binding/memory/mt8173-larb-port.h for mt8173,
dt-binding/memory/mt8183-larb-port.h for mt8183,
dt-binding/memory/mt8186-memory-port.h for mt8186,
dt-binding/memory/mt8192-larb-port.h for mt8192.
dt-binding/memory/mt8195-memory-port.h for mt8195.
power-domains:
maxItems: 1
@ -128,7 +134,6 @@ required:
- compatible
- reg
- interrupts
- mediatek,larbs
- '#iommu-cells'
allOf:
@ -140,7 +145,10 @@ allOf:
- mediatek,mt2701-m4u
- mediatek,mt2712-m4u
- mediatek,mt8173-m4u
- mediatek,mt8186-iommu-mm
- mediatek,mt8192-m4u
- mediatek,mt8195-iommu-vdo
- mediatek,mt8195-iommu-vpp
then:
required:
@ -150,12 +158,26 @@ allOf:
properties:
compatible:
enum:
- mediatek,mt8186-iommu-mm
- mediatek,mt8192-m4u
- mediatek,mt8195-iommu-vdo
- mediatek,mt8195-iommu-vpp
then:
required:
- power-domains
- if: # The IOMMUs don't have larbs.
not:
properties:
compatible:
contains:
const: mediatek,mt8195-iommu-infra
then:
required:
- mediatek,larbs
additionalProperties: false
examples:
@ -173,13 +195,3 @@ examples:
<&larb3>, <&larb4>, <&larb5>;
#iommu-cells = <1>;
};
- |
#include <dt-bindings/memory/mt8173-larb-port.h>
/* Example for a client device */
display {
compatible = "mediatek,mt8173-disp";
iommus = <&iommu M4U_PORT_DISP_OVL0>,
<&iommu M4U_PORT_DISP_RDMA0>;
};

10
Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml
View File

@ -86,16 +86,6 @@ examples:
- |
#include <dt-bindings/clock/exynos5250.h>
gsc_0: scaler@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
iommus = <&sysmmu_gsc0>;
};
sysmmu_gsc0: iommu@13e80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13E80000 0x1000>;

2
Documentation/devicetree/bindings/leds/leds-mt6360.yaml
View File

@ -43,8 +43,6 @@ patternProperties:
- 4 # LED output FLASH1
- 5 # LED output FLASH2
unevaluatedProperties: false
required:
- compatible
- "#address-cells"

2
Documentation/devicetree/bindings/mfd/atmel-flexcom.txt
View File

@ -54,7 +54,7 @@ flexcom@f8034000 {
clock-names = "spi_clk";
atmel,fifo-size = <32>;
mtd_dataflash@0 {
flash@0 {
compatible = "atmel,at25f512b";
reg = <0>;
spi-max-frequency = <20000000>;

7
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
View File

@ -202,22 +202,17 @@ allOf:
clocks:
items:
- description: module clock
minItems: 1
maxItems: 1
else:
properties:
clocks:
items:
- description: module clock
- description: timeout clock
minItems: 2
maxItems: 2
clock-names:
items:
- const: sdhci
- const: tmclk
minItems: 2
maxItems: 2
required:
- clock-names

2
Documentation/devicetree/bindings/mtd/gpmi-nand.yaml
View File

@ -147,8 +147,6 @@ allOf:
- description: SoC gpmi io clock
- description: SoC gpmi bch apb clock
clock-names:
minItems: 2
maxItems: 2
items:
- const: gpmi_io
- const: gpmi_bch_apb

3
Documentation/devicetree/bindings/net/can/bosch,c_can.yaml
View File

@ -80,8 +80,6 @@ if:
then:
properties:
interrupts:
minItems: 4
maxItems: 4
items:
- description: Error and status IRQ
- description: Message object IRQ
@ -91,7 +89,6 @@ then:
else:
properties:
interrupts:
maxItems: 1
items:
- description: Error and status IRQ

35
Documentation/devicetree/bindings/net/dsa/realtek.yaml
View File

@ -27,32 +27,25 @@ description:
The realtek-mdio driver is an MDIO driver and it must be inserted inside
an MDIO node.
The compatible string is only used to identify which (silicon) family the
switch belongs to. Roughly speaking, a family is any set of Realtek switches
whose chip identification register(s) have a common location and semantics.
The different models in a given family can be automatically disambiguated by
parsing the chip identification register(s) according to the given family,
avoiding the need for a unique compatible string for each model.
properties:
compatible:
enum:
- realtek,rtl8365mb
- realtek,rtl8366
- realtek,rtl8366rb
- realtek,rtl8366s
- realtek,rtl8367
- realtek,rtl8367b
- realtek,rtl8367rb
- realtek,rtl8367s
- realtek,rtl8368s
- realtek,rtl8369
- realtek,rtl8370
description: |
realtek,rtl8365mb: 4+1 ports
realtek,rtl8366: 5+1 ports
realtek,rtl8366rb: 5+1 ports
realtek,rtl8366s: 5+1 ports
realtek,rtl8367:
realtek,rtl8367b:
realtek,rtl8367rb: 5+2 ports
realtek,rtl8367s: 5+2 ports
realtek,rtl8368s: 8 ports
realtek,rtl8369: 8+1 ports
realtek,rtl8370: 8+2 ports
realtek,rtl8365mb:
Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
RTL8367SB, RTL8370MB, RTL8310SR
realtek,rtl8366rb:
Use with models RTL8366RB, RTL8366S
mdc-gpios:
description: GPIO line for the MDC clock line.
@ -335,7 +328,7 @@ examples:
#size-cells = <0>;
switch@29 {
compatible = "realtek,rtl8367s";
compatible = "realtek,rtl8365mb";
reg = <29>;
reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;

3
Documentation/devicetree/bindings/pci/apple,pcie.yaml
View File

@ -142,7 +142,6 @@ examples:
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
reset-gpios = <&pinctrl_ap 152 0>;
max-link-speed = <2>;
#address-cells = <3>;
#size-cells = <2>;
@ -153,7 +152,6 @@ examples:
device_type = "pci";
reg = <0x800 0x0 0x0 0x0 0x0>;
reset-gpios = <&pinctrl_ap 153 0>;
max-link-speed = <2>;
#address-cells = <3>;
#size-cells = <2>;
@ -164,7 +162,6 @@ examples:
device_type = "pci";
reg = <0x1000 0x0 0x0 0x0 0x0>;
reset-gpios = <&pinctrl_ap 33 0>;
max-link-speed = <1>;
#address-cells = <3>;
#size-cells = <2>;

10
Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml
View File

@ -102,19 +102,17 @@ if:
then:
properties:
reg:
maxItems: 2
minItems: 2
reg-names:
items:
- const: "phy"
- const: "phy-ctrl"
minItems: 2
else:
properties:
reg:
maxItems: 1
reg-names:
maxItems: 1
items:
- const: "phy"
required:
- compatible

12
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
View File

@ -52,11 +52,19 @@ properties:
hardware supporting it the pull strength in Ohm.
drive-push-pull:
type: boolean
oneOf:
- type: boolean
- $ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1 ]
deprecated: true
description: drive actively high and low
drive-open-drain:
type: boolean
oneOf:
- type: boolean
- $ref: /schemas/types.yaml#/definitions/uint32
const: 1 # No known cases of 0
deprecated: true
description: drive with open drain
drive-open-source:

2
Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml
View File

@ -58,7 +58,7 @@ properties:
type: object
$ref: regulator.yaml#
description: |
regulator description for buck1 and buck4.
regulator description for buck1 to buck4, and ldo.
properties:
regulator-allowed-modes:

10
Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
View File

@ -71,7 +71,6 @@ allOf:
then:
properties:
clock-output-names:
minItems: 1
maxItems: 1
- if:
@ -102,7 +101,6 @@ allOf:
properties:
clock-output-names:
minItems: 3
maxItems: 3
- if:
properties:
@ -113,16 +111,12 @@ allOf:
then:
properties:
clocks:
minItems: 3
maxItems: 3
items:
- description: Bus clock for register access
- description: 24 MHz oscillator
- description: 32 kHz clock from the CCU
clock-names:
minItems: 3
maxItems: 3
items:
- const: bus
- const: hosc
@ -142,7 +136,6 @@ allOf:
properties:
clocks:
minItems: 3
maxItems: 4
items:
- description: Bus clock for register access
- description: 24 MHz oscillator
@ -151,7 +144,6 @@ allOf:
clock-names:
minItems: 3
maxItems: 4
items:
- const: bus
- const: hosc
@ -174,14 +166,12 @@ allOf:
then:
properties:
interrupts:
minItems: 1
maxItems: 1
else:
properties:
interrupts:
minItems: 2
maxItems: 2
required:
- "#clock-cells"

15
Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
View File

@ -31,11 +31,19 @@ properties:
to that of the RTC's count register.
clocks:
maxItems: 1
items:
- description: |
AHB clock
- description: |
Reference clock: divided by the prescaler to create a time-based
strobe (typically 1 Hz) for the calendar counter. By default, the rtc
on the PolarFire SoC shares it's reference with MTIMER so this will
be a 1 MHz clock.
clock-names:
items:
- const: rtc
- const: rtcref
required:
- compatible
@ -48,11 +56,12 @@ additionalProperties: false
examples:
- |
#include "dt-bindings/clock/microchip,mpfs-clock.h"
rtc@20124000 {
compatible = "microchip,mpfs-rtc";
reg = <0x20124000 0x1000>;
clocks = <&clkcfg 21>;
clock-names = "rtc";
clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
clock-names = "rtc", "rtcref";
interrupts = <80>, <81>;
};
...

4
Documentation/devicetree/bindings/serial/samsung_uart.yaml
View File

@ -100,7 +100,6 @@ allOf:
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
items:
- const: uart
- pattern: '^clk_uart_baud[0-1]$'
@ -118,11 +117,8 @@ allOf:
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
minItems: 2
maxItems: 2
items:
- const: uart
- const: clk_uart_baud0

1
Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-i2s.yaml
View File

@ -89,7 +89,6 @@ allOf:
properties:
dmas:
minItems: 1
maxItems: 2
items:
- description: RX DMA Channel
- description: TX DMA Channel

2
Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml
View File

@ -80,7 +80,6 @@ allOf:
then:
properties:
clocks:
minItems: 6
items:
- description: AUXCLK clock for McASP used by CPB audio
- description: Parent for CPB_McASP auxclk (for 48KHz)
@ -107,7 +106,6 @@ allOf:
then:
properties:
clocks:
maxItems: 4
items:
- description: AUXCLK clock for McASP used by CPB audio
- description: Parent for CPB_McASP auxclk (for 48KHz)

1
Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml
View File

@ -67,7 +67,6 @@ then:
properties:
reg:
minItems: 2
maxItems: 3
items:
- description: TSC1 registers
- description: TSC2 registers

3
Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml
View File

@ -43,6 +43,9 @@ properties:
- const: phy_clk
- const: ref_clk
power-domains:
maxItems: 1
reg:
maxItems: 1

1
Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml
View File

@ -62,6 +62,7 @@ required:
- interrupts
- phys
- phy-names
- reg
allOf:
- if:

70
Documentation/filesystems/f2fs.rst
View File

@ -235,12 +235,6 @@ offgrpjquota Turn off group journalled quota.
offprjjquota Turn off project journalled quota.
quota Enable plain user disk quota accounting.
noquota Disable all plain disk quota option.
whint_mode=%s Control which write hints are passed down to block
layer. This supports "off", "user-based", and
"fs-based". In "off" mode (default), f2fs does not pass
down hints. In "user-based" mode, f2fs tries to pass
down hints given by users. And in "fs-based" mode, f2fs
passes down hints with its policy.
alloc_mode=%s Adjust block allocation policy, which supports "reuse"
and "default".
fsync_mode=%s Control the policy of fsync. Currently supports "posix",
@ -751,70 +745,6 @@ In order to identify whether the data in the victim segment are valid or not,
F2FS manages a bitmap. Each bit represents the validity of a block, and the
bitmap is composed of a bit stream covering whole blocks in main area.
Write-hint Policy
-----------------
1) whint_mode=off. F2FS only passes down WRITE_LIFE_NOT_SET.
2) whint_mode=user-based. F2FS tries to pass down hints given by
users.
===================== ======================== ===================
User F2FS Block
===================== ======================== ===================
N/A META WRITE_LIFE_NOT_SET
N/A HOT_NODE "
N/A WARM_NODE "
N/A COLD_NODE "
ioctl(COLD) COLD_DATA WRITE_LIFE_EXTREME
extension list " "
-- buffered io
WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_NOT_SET
WRITE_LIFE_NONE " "
WRITE_LIFE_MEDIUM " "
WRITE_LIFE_LONG " "
-- direct io
WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_NOT_SET
WRITE_LIFE_NONE " WRITE_LIFE_NONE
WRITE_LIFE_MEDIUM " WRITE_LIFE_MEDIUM
WRITE_LIFE_LONG " WRITE_LIFE_LONG
===================== ======================== ===================
3) whint_mode=fs-based. F2FS passes down hints with its policy.
===================== ======================== ===================
User F2FS Block
===================== ======================== ===================
N/A META WRITE_LIFE_MEDIUM;
N/A HOT_NODE WRITE_LIFE_NOT_SET
N/A WARM_NODE "
N/A COLD_NODE WRITE_LIFE_NONE
ioctl(COLD) COLD_DATA WRITE_LIFE_EXTREME
extension list " "
-- buffered io
WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_LONG
WRITE_LIFE_NONE " "
WRITE_LIFE_MEDIUM " "
WRITE_LIFE_LONG " "
-- direct io
WRITE_LIFE_EXTREME COLD_DATA WRITE_LIFE_EXTREME
WRITE_LIFE_SHORT HOT_DATA WRITE_LIFE_SHORT
WRITE_LIFE_NOT_SET WARM_DATA WRITE_LIFE_NOT_SET
WRITE_LIFE_NONE " WRITE_LIFE_NONE
WRITE_LIFE_MEDIUM " WRITE_LIFE_MEDIUM
WRITE_LIFE_LONG " WRITE_LIFE_LONG
===================== ======================== ===================
Fallocate(2) Policy
-------------------

7
Documentation/process/embargoed-hardware-issues.rst
View File

@ -244,10 +244,11 @@ disclosure of a particular issue, unless requested by a response team or by
an involved disclosed party. The current ambassadors list:
============= ========================================================
ARM Grant Likely <grant.likely@arm.com>
AMD Tom Lendacky <tom.lendacky@amd.com>
IBM Z Christian Borntraeger <borntraeger@de.ibm.com>
IBM Power Anton Blanchard <anton@linux.ibm.com>
Ampere Darren Hart <darren@os.amperecomputing.com>
ARM Catalin Marinas <catalin.marinas@arm.com>
IBM Power Anton Blanchard <anton@linux.ibm.com>
IBM Z Christian Borntraeger <borntraeger@de.ibm.com>
Intel Tony Luck <tony.luck@intel.com>
Qualcomm Trilok Soni <tsoni@codeaurora.org>

42
Documentation/security/siphash.rst
View File

@ -121,26 +121,36 @@ even scarier, uses an easily brute-forcable 64-bit key (with a 32-bit output)
instead of SipHash's 128-bit key. However, this may appeal to some
high-performance `jhash` users.
Danger!
HalfSipHash support is provided through the "hsiphash" family of functions.
Do not ever use HalfSipHash except for as a hashtable key function, and only
then when you can be absolutely certain that the outputs will never be
transmitted out of the kernel. This is only remotely useful over `jhash` as a
means of mitigating hashtable flooding denial of service attacks.
.. warning::
Do not ever use the hsiphash functions except for as a hashtable key
function, and only then when you can be absolutely certain that the outputs
will never be transmitted out of the kernel. This is only remotely useful
over `jhash` as a means of mitigating hashtable flooding denial of service
attacks.
Generating a HalfSipHash key
============================
On 64-bit kernels, the hsiphash functions actually implement SipHash-1-3, a
reduced-round variant of SipHash, instead of HalfSipHash-1-3. This is because in
64-bit code, SipHash-1-3 is no slower than HalfSipHash-1-3, and can be faster.
Note, this does *not* mean that in 64-bit kernels the hsiphash functions are the
same as the siphash ones, or that they are secure; the hsiphash functions still
use a less secure reduced-round algorithm and truncate their outputs to 32
bits.
Generating a hsiphash key
=========================
Keys should always be generated from a cryptographically secure source of
random numbers, either using get_random_bytes or get_random_once:
random numbers, either using get_random_bytes or get_random_once::
hsiphash_key_t key;
get_random_bytes(&key, sizeof(key));
hsiphash_key_t key;
get_random_bytes(&key, sizeof(key));
If you're not deriving your key from here, you're doing it wrong.
Using the HalfSipHash functions
===============================
Using the hsiphash functions
============================
There are two variants of the function, one that takes a list of integers, and
one that takes a buffer::
@ -183,7 +193,7 @@ You may then iterate like usual over the returned hash bucket.
Performance
===========
HalfSipHash is roughly 3 times slower than JenkinsHash. For many replacements,
this will not be a problem, as the hashtable lookup isn't the bottleneck. And
in general, this is probably a good sacrifice to make for the security and DoS
resistance of HalfSipHash.
hsiphash() is roughly 3 times slower than jhash(). For many replacements, this
will not be a problem, as the hashtable lookup isn't the bottleneck. And in
general, this is probably a good sacrifice to make for the security and DoS
resistance of hsiphash().

24
Documentation/virt/kvm/api.rst
View File

@ -5986,16 +5986,16 @@ should put the acknowledged interrupt vector into the 'epr' field.
#define KVM_SYSTEM_EVENT_RESET 2
#define KVM_SYSTEM_EVENT_CRASH 3
__u32 type;
__u64 flags;
__u32 ndata;
__u64 data[16];
} system_event;
If exit_reason is KVM_EXIT_SYSTEM_EVENT then the vcpu has triggered
a system-level event using some architecture specific mechanism (hypercall
or some special instruction). In case of ARM64, this is triggered using
HVC instruction based PSCI call from the vcpu. The 'type' field describes
the system-level event type. The 'flags' field describes architecture
specific flags for the system-level event.
HVC instruction based PSCI call from the vcpu.
The 'type' field describes the system-level event type.
Valid values for 'type' are:
- KVM_SYSTEM_EVENT_SHUTDOWN -- the guest has requested a shutdown of the
@ -6010,10 +6010,20 @@ Valid values for 'type' are:
to ignore the request, or to gather VM memory core dump and/or
reset/shutdown of the VM.
Valid flags are:
If KVM_CAP_SYSTEM_EVENT_DATA is present, the 'data' field can contain
architecture specific information for the system-level event. Only
the first `ndata` items (possibly zero) of the data array are valid.
- KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (arm64 only) -- the guest issued
a SYSTEM_RESET2 call according to v1.1 of the PSCI specification.
- for arm64, data[0] is set to KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 if
the guest issued a SYSTEM_RESET2 call according to v1.1 of the PSCI
specification.
- for RISC-V, data[0] is set to the value of the second argument of the
``sbi_system_reset`` call.
Previous versions of Linux defined a `flags` member in this struct. The
field is now aliased to `data[0]`. Userspace can assume that it is only
written if ndata is greater than 0.
::

5
Documentation/vm/page_owner.rst
View File

@ -110,7 +110,7 @@ Usage
If you want to sort by the page nums of buf, use the ``-m`` parameter.
The detailed parameters are:
fundamental function:
fundamental function::
Sort:
-a Sort by memory allocation time.
@ -122,7 +122,7 @@ Usage
-s Sort by stack trace.
-t Sort by times (default).
additional function:
additional function::
Cull:
--cull <rules>
@ -153,6 +153,7 @@ Usage
STANDARD FORMAT SPECIFIERS
==========================
::
KEY LONG DESCRIPTION
p pid process ID

52
MAINTAINERS
View File

@ -2638,6 +2638,7 @@ L: linux-samsung-soc@vger.kernel.org
S: Maintained
C: irc://irc.libera.chat/linux-exynos
Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
B: mailto:linux-samsung-soc@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
F: Documentation/arm/samsung/
F: Documentation/devicetree/bindings/arm/samsung/
@ -3564,8 +3565,9 @@ M: Andy Gospodarek <andy@greyhouse.net>
L: netdev@vger.kernel.org
S: Supported
W: http://sourceforge.net/projects/bonding/
F: Documentation/networking/bonding.rst
F: drivers/net/bonding/
F: include/net/bonding.h
F: include/net/bond*
F: include/uapi/linux/if_bonding.h
BOSCH SENSORTEC BMA400 ACCELEROMETER IIO DRIVER
@ -3907,7 +3909,9 @@ BROADCOM BNXT_EN 50 GIGABIT ETHERNET DRIVER
M: Michael Chan <michael.chan@broadcom.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/firmware/broadcom/tee_bnxt_fw.c
F: drivers/net/ethernet/broadcom/bnxt/
F: include/linux/firmware/broadcom/tee_bnxt_fw.h
BROADCOM BRCM80211 IEEE802.11n WIRELESS DRIVER
M: Arend van Spriel <aspriel@gmail.com>
@ -5430,6 +5434,7 @@ F: net/ax25/sysctl_net_ax25.c
DATA ACCESS MONITOR
M: SeongJae Park <sj@kernel.org>
L: damon@lists.linux.dev
L: linux-mm@kvack.org
S: Maintained
F: Documentation/ABI/testing/sysfs-kernel-mm-damon
@ -5908,7 +5913,7 @@ R: Benjamin Gaignard <benjamin.gaignard@collabora.com>
R: Liam Mark <lmark@codeaurora.org>
R: Laura Abbott <labbott@redhat.com>
R: Brian Starkey <Brian.Starkey@arm.com>
R: John Stultz <john.stultz@linaro.org>
R: John Stultz <jstultz@google.com>
L: linux-media@vger.kernel.org
L: dri-devel@lists.freedesktop.org
L: linaro-mm-sig@lists.linaro.org (moderated for non-subscribers)
@ -6578,7 +6583,7 @@ F: drivers/gpu/drm/gma500/
DRM DRIVERS FOR HISILICON
M: Xinliang Liu <xinliang.liu@linaro.org>
M: Tian Tao <tiantao6@hisilicon.com>
R: John Stultz <john.stultz@linaro.org>
R: John Stultz <jstultz@google.com>
R: Xinwei Kong <kong.kongxinwei@hisilicon.com>
R: Chen Feng <puck.chen@hisilicon.com>
L: dri-devel@lists.freedesktop.org
@ -7490,7 +7495,7 @@ F: Documentation/hwmon/f71805f.rst
F: drivers/hwmon/f71805f.c
FADDR2LINE
M: Josh Poimboeuf <jpoimboe@redhat.com>
M: Josh Poimboeuf <jpoimboe@kernel.org>
S: Maintained
F: scripts/faddr2line
@ -8103,7 +8108,7 @@ M: Ingo Molnar <mingo@redhat.com>
R: Peter Zijlstra <peterz@infradead.org>
R: Darren Hart <dvhart@infradead.org>
R: Davidlohr Bueso <dave@stgolabs.net>
R: André Almeida <andrealmeid@collabora.com>
R: André Almeida <andrealmeid@igalia.com>
L: linux-kernel@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git locking/core
@ -8376,7 +8381,7 @@ M: Linus Walleij <linus.walleij@linaro.org>
M: Bartosz Golaszewski <brgl@bgdev.pl>
L: linux-gpio@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git
F: Documentation/ABI/obsolete/sysfs-gpio
F: Documentation/ABI/testing/gpio-cdev
F: Documentation/admin-guide/gpio/
@ -8839,7 +8844,7 @@ F: Documentation/devicetree/bindings/net/hisilicon*.txt
F: drivers/net/ethernet/hisilicon/
HIKEY960 ONBOARD USB GPIO HUB DRIVER
M: John Stultz <john.stultz@linaro.org>
M: John Stultz <jstultz@google.com>
L: linux-kernel@vger.kernel.org
S: Maintained
F: drivers/misc/hisi_hikey_usb.c
@ -10122,7 +10127,7 @@ S: Supported
F: drivers/net/wireless/intel/iwlegacy/
INTEL WIRELESS WIFI LINK (iwlwifi)
M: Luca Coelho <luciano.coelho@intel.com>
M: Gregory Greenman <gregory.greenman@intel.com>
L: linux-wireless@vger.kernel.org
S: Supported
W: https://wireless.wiki.kernel.org/en/users/drivers/iwlwifi
@ -10231,8 +10236,6 @@ F: drivers/net/ethernet/sgi/ioc3-eth.c
IOMAP FILESYSTEM LIBRARY
M: Christoph Hellwig <hch@infradead.org>
M: Darrick J. Wong <djwong@kernel.org>
M: linux-xfs@vger.kernel.org
M: linux-fsdevel@vger.kernel.org
L: linux-xfs@vger.kernel.org
L: linux-fsdevel@vger.kernel.org
S: Supported
@ -11341,7 +11344,7 @@ F: drivers/mmc/host/litex_mmc.c
N: litex
LIVE PATCHING
M: Josh Poimboeuf <jpoimboe@redhat.com>
M: Josh Poimboeuf <jpoimboe@kernel.org>
M: Jiri Kosina <jikos@kernel.org>
M: Miroslav Benes <mbenes@suse.cz>
M: Petr Mladek <pmladek@suse.com>
@ -11967,6 +11970,7 @@ M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
L: linux-pm@vger.kernel.org
S: Supported
B: mailto:linux-samsung-soc@vger.kernel.org
F: Documentation/devicetree/bindings/power/supply/maxim,max14577.yaml
F: Documentation/devicetree/bindings/power/supply/maxim,max77693.yaml
F: drivers/power/supply/max14577_charger.c
@ -11978,6 +11982,7 @@ M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
L: linux-kernel@vger.kernel.org
S: Supported
B: mailto:linux-samsung-soc@vger.kernel.org
F: Documentation/devicetree/bindings/*/maxim,max14577.yaml
F: Documentation/devicetree/bindings/*/maxim,max77686.yaml
F: Documentation/devicetree/bindings/*/maxim,max77693.yaml
@ -12671,6 +12676,7 @@ MEMORY CONTROLLER DRIVERS
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
L: linux-kernel@vger.kernel.org
S: Maintained
B: mailto:krzysztof.kozlowski@linaro.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git
F: Documentation/devicetree/bindings/memory-controllers/
F: drivers/memory/
@ -13619,6 +13625,7 @@ F: net/core/drop_monitor.c
NETWORKING DRIVERS
M: "David S. Miller" <davem@davemloft.net>
M: Eric Dumazet <edumazet@google.com>
M: Jakub Kicinski <kuba@kernel.org>
M: Paolo Abeni <pabeni@redhat.com>
L: netdev@vger.kernel.org
@ -13666,6 +13673,7 @@ F: tools/testing/selftests/drivers/net/dsa/
NETWORKING [GENERAL]
M: "David S. Miller" <davem@davemloft.net>
M: Eric Dumazet <edumazet@google.com>
M: Jakub Kicinski <kuba@kernel.org>
M: Paolo Abeni <pabeni@redhat.com>
L: netdev@vger.kernel.org
@ -14212,7 +14220,7 @@ F: lib/objagg.c
F: lib/test_objagg.c
OBJTOOL
M: Josh Poimboeuf <jpoimboe@redhat.com>
M: Josh Poimboeuf <jpoimboe@kernel.org>
M: Peter Zijlstra <peterz@infradead.org>
S: Supported
F: tools/objtool/
@ -15463,7 +15471,8 @@ F: tools/perf/
PERFORMANCE EVENTS TOOLING ARM64
R: John Garry <john.garry@huawei.com>
R: Will Deacon <will@kernel.org>
R: Mathieu Poirier <mathieu.poirier@linaro.org>
R: James Clark <james.clark@arm.com>
R: Mike Leach <mike.leach@linaro.org>
R: Leo Yan <leo.yan@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
@ -15603,6 +15612,7 @@ L: linux-samsung-soc@vger.kernel.org
S: Maintained
C: irc://irc.libera.chat/linux-exynos
Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
B: mailto:linux-samsung-soc@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git
F: Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml
F: drivers/pinctrl/samsung/
@ -17319,6 +17329,7 @@ M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Supported
B: mailto:linux-samsung-soc@vger.kernel.org
F: Documentation/devicetree/bindings/sound/samsung*
F: sound/soc/samsung/
@ -17363,6 +17374,7 @@ M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
L: linux-kernel@vger.kernel.org
L: linux-samsung-soc@vger.kernel.org
S: Supported
B: mailto:linux-samsung-soc@vger.kernel.org
F: Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
F: Documentation/devicetree/bindings/mfd/samsung,s2m*.yaml
F: Documentation/devicetree/bindings/mfd/samsung,s5m*.yaml
@ -18777,7 +18789,7 @@ F: include/dt-bindings/reset/starfive-jh7100.h
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@redhat.com>
M: Josh Poimboeuf <jpoimboe@kernel.org>
M: Jason Baron <jbaron@akamai.com>
R: Steven Rostedt <rostedt@goodmis.org>
R: Ard Biesheuvel <ardb@kernel.org>
@ -19778,7 +19790,7 @@ F: drivers/net/wireless/ti/
F: include/linux/wl12xx.h
TIMEKEEPING, CLOCKSOURCE CORE, NTP, ALARMTIMER
M: John Stultz <john.stultz@linaro.org>
M: John Stultz <jstultz@google.com>
M: Thomas Gleixner <tglx@linutronix.de>
R: Stephen Boyd <sboyd@kernel.org>
L: linux-kernel@vger.kernel.org
@ -21428,6 +21440,15 @@ F: arch/x86/include/asm/uv/
F: arch/x86/kernel/apic/x2apic_uv_x.c
F: arch/x86/platform/uv/
X86 STACK UNWINDING
M: Josh Poimboeuf <jpoimboe@kernel.org>
M: Peter Zijlstra <peterz@infradead.org>
S: Supported
F: arch/x86/include/asm/unwind*.h
F: arch/x86/kernel/dumpstack.c
F: arch/x86/kernel/stacktrace.c
F: arch/x86/kernel/unwind_*.c
X86 VDSO
M: Andy Lutomirski <luto@kernel.org>
L: linux-kernel@vger.kernel.org
@ -21590,7 +21611,6 @@ F: drivers/xen/*swiotlb*
XFS FILESYSTEM
C: irc://irc.oftc.net/xfs
M: Darrick J. Wong <djwong@kernel.org>
M: linux-xfs@vger.kernel.org
L: linux-xfs@vger.kernel.org
S: Supported
W: http://xfs.org/

2
Makefile
View File

@ -2,7 +2,7 @@
VERSION = 5
PATCHLEVEL = 18
SUBLEVEL = 0
EXTRAVERSION = -rc4
EXTRAVERSION = -rc7
NAME = Superb Owl
# *DOCUMENTATION*

2
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -263,6 +263,8 @@
compatible = "ti,am3359-tscadc";
reg = <0x0 0x1000>;
interrupts = <16>;
clocks = <&adc_tsc_fck>;
clock-names = "fck";
status = "disabled";
dmas = <&edma 53 0>, <&edma 57 0>;
dma-names = "fifo0", "fifo1";

45
arch/arm/boot/dts/am3517-evm.dts
View File

@ -161,6 +161,8 @@
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_rst_pins>;
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
#phy-cells = <0>;
@ -168,7 +170,9 @@
};
&davinci_emac {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ethernet_pins>;
status = "okay";
};
&davinci_mdio {
@ -193,6 +197,8 @@
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
/* User DIP swithes [1:8] / User LEDS [1:2] */
tca6416: gpio@21 {
@ -205,6 +211,8 @@
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
};
@ -223,6 +231,8 @@
};
&usbhshost {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_pins>;
port1-mode = "ehci-phy";
};
@ -231,8 +241,35 @@
};
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_rst_pins>;
ethernet_pins: pinmux_ethernet_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */
OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */
OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */
OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */
OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */
OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */
OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */
OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */
OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */
OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
@ -300,8 +337,6 @@
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_pins>;
hsusb1_pins: pinmux_hsusb1_pins {
pinctrl-single,pins = <

9
arch/arm/boot/dts/am3517-som.dtsi
View File

@ -69,6 +69,8 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
s35390a: s35390a@30 {
@ -179,6 +181,13 @@
&omap3_pmx_core {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
>;
};
wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */

2
arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
View File

@ -44,7 +44,7 @@
status = "okay";
/* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */
spi-flash@0 {
flash@0 {
compatible = "mxicy,mx25u4035", "jedec,spi-nor";
spi-max-frequency = <33000000>;
reg = <0>;

2
arch/arm/boot/dts/at91-kizbox3-hs.dts
View File

@ -225,7 +225,7 @@
pinctrl_pio_io_reset: gpio_io_reset {
pinmux = <PIN_PB30__GPIO>;
bias-disable;
drive-open-drain;
drive-open-drain = <1>;
output-low;
};
pinctrl_pio_input: gpio_input {

2
arch/arm/boot/dts/at91-kizbox3_common.dtsi
View File

@ -211,7 +211,7 @@
pinmux = <PIN_PD12__FLEXCOM4_IO0>, //DATA
<PIN_PD13__FLEXCOM4_IO1>; //CLK
bias-disable;
drive-open-drain;
drive-open-drain = <1>;
};
pinctrl_pwm0 {

2
arch/arm/boot/dts/at91-q5xr5.dts
View File

@ -125,7 +125,7 @@
cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
status = "okay";
m25p80@0 {
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;

2
arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
View File

@ -214,7 +214,7 @@
pinctrl-0 = <&pinctrl_qspi1_default>;
status = "disabled";
qspi1_flash: spi_flash@0 {
qspi1_flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

2
arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
View File

@ -191,7 +191,7 @@
&qspi1 {
status = "okay";
qspi1_flash: spi_flash@0 {
qspi1_flash: flash@0 {
status = "okay";
};
};

2
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@ -137,7 +137,7 @@
pinctrl-0 = <&pinctrl_spi0_default>;
status = "okay";
m25p80@0 {
flash@0 {
compatible = "atmel,at25df321a";
reg = <0>;
spi-max-frequency = <50000000>;

8
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View File

@ -57,8 +57,8 @@
};
spi0: spi@f0004000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_cs>;
pinctrl-names = "default", "cs";
pinctrl-1 = <&pinctrl_spi0_cs>;
cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
status = "okay";
};
@ -171,8 +171,8 @@
};
spi1: spi@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_cs>;
pinctrl-names = "default", "cs";
pinctrl-1 = <&pinctrl_spi1_cs>;
cs-gpios = <&pioC 25 0>;
status = "okay";
};

2
arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
View File

@ -49,7 +49,7 @@
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
m25p80@0 {
flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;

6
arch/arm/boot/dts/at91-sama5d4_xplained.dts
View File

@ -81,8 +81,8 @@
};
spi1: spi@fc018000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_cs>;
pinctrl-names = "default", "cs";
pinctrl-1 = <&pinctrl_spi1_cs>;
cs-gpios = <&pioB 21 0>;
status = "okay";
};
@ -140,7 +140,7 @@
atmel,pins =
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_spi0_cs: spi0_cs_default {
pinctrl_spi1_cs: spi1_cs_default {
atmel,pins =
<AT91_PIOB 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};

2
arch/arm/boot/dts/at91-sama5d4ek.dts
View File

@ -65,7 +65,7 @@
spi0: spi@f8010000 {
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
m25p80@0 {
flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;

4
arch/arm/boot/dts/at91-sama7g5ek.dts
View File

@ -495,7 +495,7 @@
pinctrl_flx3_default: flx3_default {
pinmux = <PIN_PD16__FLEXCOM3_IO0>,
<PIN_PD17__FLEXCOM3_IO1>;
bias-disable;
bias-pull-up;
};
pinctrl_flx4_default: flx4_default {
@ -655,7 +655,7 @@
<PIN_PB21__QSPI0_INT>;
bias-disable;
slew-rate = <0>;
atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;
atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
};
pinctrl_sdmmc0_default: sdmmc0_default {

2
arch/arm/boot/dts/at91-vinco.dts
View File

@ -59,7 +59,7 @@
spi0: spi@f8010000 {
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
m25p80@0 {
flash@0 {
compatible = "n25q32b", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;

4
arch/arm/boot/dts/at91rm9200ek.dts
View File

@ -73,7 +73,7 @@
spi0: spi@fffe0000 {
status = "okay";
cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
mtd_dataflash@0 {
flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <15000000>;
reg = <0>;
@ -94,7 +94,7 @@
status = "okay";
};
nor_flash@10000000 {
flash@10000000 {
compatible = "cfi-flash";
reg = <0x10000000 0x800000>;
linux,mtd-name = "physmap-flash.0";

2
arch/arm/boot/dts/at91sam9260ek.dts
View File

@ -92,7 +92,7 @@
spi0: spi@fffc8000 {
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
mtd_dataflash@1 {
flash@1 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
reg = <1>;

2
arch/arm/boot/dts/at91sam9261ek.dts
View File

@ -145,7 +145,7 @@
cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>;
status = "okay";
mtd_dataflash@0 {
flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
reg = <0>;
spi-max-frequency = <15000000>;

2
arch/arm/boot/dts/at91sam9263ek.dts
View File

@ -95,7 +95,7 @@
spi0: spi@fffa4000 {
status = "okay";
cs-gpios = <&pioA 5 0>, <0>, <0>, <0>;
mtd_dataflash@0 {
flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
reg = <0>;

45
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
View File

@ -110,7 +110,7 @@
spi0: spi@fffc8000 {
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
mtd_dataflash@1 {
flash@1 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
reg = <1>;
@ -214,11 +214,23 @@
24c512@50 {
compatible = "atmel,24c512";
reg = <0x50>;
vcc-supply = <&reg_3v3>;
};
wm8731: wm8731@1b {
compatible = "wm8731";
reg = <0x1b>;
/* PCK0 at 12MHz */
clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "mclk";
assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
assigned-clock-rates = <12000000>;
HPVDD-supply = <&vcc_dac>;
AVDD-supply = <&vcc_dac>;
DCVDD-supply = <&reg_3v3>;
DBVDD-supply = <&reg_3v3>;
};
};
@ -254,4 +266,35 @@
atmel,ssc-controller = <&ssc0>;
atmel,audio-codec = <&wm8731>;
};
reg_5v: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_3v3: fixedregulator1 {
compatible = "regulator-fixed";
regulator-name = "3V3";
vin-supply = <&reg_5v>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_1v: fixedregulator2 {
compatible = "regulator-fixed";
regulator-name = "1V";
vin-supply = <&reg_5v>;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vcc_dac: fixedregulator3 {
compatible = "regulator-fixed";
regulator-name = "VCC_DAC";
vin-supply = <&reg_3v3>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};

2
arch/arm/boot/dts/at91sam9m10g45ek.dts
View File

@ -167,7 +167,7 @@
spi0: spi@fffa4000{
status = "okay";
cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
mtd_dataflash@0 {
flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <13000000>;
reg = <0>;

2
arch/arm/boot/dts/at91sam9n12ek.dts
View File

@ -119,7 +119,7 @@
spi0: spi@f0000000 {
status = "okay";
cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
m25p80@0 {
flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;

2
arch/arm/boot/dts/at91sam9rlek.dts
View File

@ -180,7 +180,7 @@
spi0: spi@fffcc000 {
status = "okay";
cs-gpios = <&pioA 28 0>, <0>, <0>, <0>;
mtd_dataflash@0 {
flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <15000000>;
reg = <0>;

2
arch/arm/boot/dts/at91sam9x5ek.dtsi
View File

@ -125,7 +125,7 @@
cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
status = "disabled"; /* conflicts with mmc1 */
m25p80@0 {
flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;

4
arch/arm/boot/dts/dra7-l4.dtsi
View File

@ -4188,11 +4188,11 @@
reg = <0x1d0010 0x4>;
reg-names = "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
<SYSC_IDLE_NO>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
power-domains = <&prm_vpe>;
clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;

10
arch/arm/boot/dts/imx6qdl-apalis.dtsi
View File

@ -286,6 +286,8 @@
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sgtl5000>;
clocks = <&clks IMX6QDL_CLK_CKO>;
VDDA-supply = <&reg_module_3v3_audio>;
VDDIO-supply = <&reg_module_3v3>;
@ -517,8 +519,6 @@
MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
/* SGTL5000 sys_mclk */
MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
>;
};
@ -811,6 +811,12 @@
>;
};
pinctrl_sgtl5000: sgtl5000grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0

2
arch/arm/boot/dts/imx6ull-colibri.dtsi
View File

@ -37,7 +37,7 @@
reg_sd1_vmmc: regulator-sd1-vmmc {
compatible = "regulator-gpio";
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_reg_sd>;
regulator-always-on;

15
arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
View File

@ -11,3 +11,18 @@
model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3";
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <&hsusb2_2_pins>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
};

15
arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts
View File

@ -11,3 +11,18 @@
model = "LogicPD Zoom DM3730 SOM-LV Development Kit";
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <&hsusb2_2_pins>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
};

15
arch/arm/boot/dts/logicpd-som-lv.dtsi
View File

@ -265,21 +265,6 @@
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <&hsusb2_2_pins>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
};
&uart2 {
interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
pinctrl-names = "default";

2
arch/arm/boot/dts/omap3-gta04.dtsi
View File

@ -31,6 +31,8 @@
aliases {
display0 = &lcd;
display1 = &tv0;
/delete-property/ mmc2;
/delete-property/ mmc3;
};
ldo_3v3: fixedregulator {

2
arch/arm/boot/dts/sama5d3xmb.dtsi
View File

@ -26,7 +26,7 @@
spi0: spi@f0004000 {
dmas = <0>, <0>; /* Do not use DMA for spi0 */
m25p80@0 {
flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;

2
arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
View File

@ -25,7 +25,7 @@
spi0: spi@f0004000 {
dmas = <0>, <0>; /* Do not use DMA for spi0 */
m25p80@0 {
flash@0 {
compatible = "atmel,at25df321a";
spi-max-frequency = <50000000>;
reg = <0>;

18
arch/arm/boot/dts/sama7g5.dtsi
View File

@ -601,9 +601,9 @@
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
<&dma0 AT91_XDMAC_DT_PERID(8)>;
dma-names = "rx", "tx";
dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
<&dma0 AT91_XDMAC_DT_PERID(7)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
@ -786,9 +786,9 @@
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,
<&dma0 AT91_XDMAC_DT_PERID(22)>;
dma-names = "rx", "tx";
dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
<&dma0 AT91_XDMAC_DT_PERID(21)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
@ -810,9 +810,9 @@
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>,
<&dma0 AT91_XDMAC_DT_PERID(24)>;
dma-names = "rx", "tx";
dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
<&dma0 AT91_XDMAC_DT_PERID(23)>;
dma-names = "tx", "rx";
status = "disabled";
};
};

2
arch/arm/boot/dts/usb_a9263.dts
View File

@ -60,7 +60,7 @@
spi0: spi@fffa4000 {
cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;
status = "okay";
mtd_dataflash@0 {
flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
reg = <0>;
spi-max-frequency = <15000000>;

1
arch/arm/configs/multi_v7_defconfig
View File

@ -673,6 +673,7 @@ CONFIG_VIDEO_STI_DELTA=m
CONFIG_VIDEO_RENESAS_FDP1=m
CONFIG_VIDEO_RENESAS_JPU=m
CONFIG_VIDEO_RENESAS_VSP1=m
CONFIG_VIDEO_TEGRA_VDE=m
CONFIG_V4L_TEST_DRIVERS=y
CONFIG_VIDEO_VIVID=m
CONFIG_VIDEO_ADV7180=m

3
arch/arm/configs/tegra_defconfig
View File

@ -286,7 +286,8 @@ CONFIG_SERIO_NVEC_PS2=y
CONFIG_NVEC_POWER=y
CONFIG_NVEC_PAZ00=y
CONFIG_STAGING_MEDIA=y
CONFIG_TEGRA_VDE=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_TEGRA_VDE=y
CONFIG_CHROME_PLATFORMS=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_I2C=m

3
arch/arm/include/asm/io.h
View File

@ -440,6 +440,9 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
unsigned long flags);
#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
#endif
/*

1
arch/arm/mach-exynos/Kconfig
View File

@ -17,7 +17,6 @@ menuconfig ARCH_EXYNOS
select EXYNOS_PMU
select EXYNOS_SROM
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
select GPIOLIB
select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5
select HAVE_ARM_SCU if SMP
select PINCTRL

2
arch/arm/mach-omap2/omap4-common.c
View File

@ -314,10 +314,12 @@ void __init omap_gic_of_init(void)
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
gic_dist_base_addr = of_iomap(np, 0);
of_node_put(np);
WARN_ON(!gic_dist_base_addr);
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
twd_base = of_iomap(np, 0);
of_node_put(np);
WARN_ON(!twd_base);
skip_errata_init:

8
arch/arm/mm/ioremap.c
View File

@ -493,3 +493,11 @@ void __init early_ioremap_init(void)
{
early_ioremap_setup();
}
bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
unsigned long flags)
{
unsigned long pfn = PHYS_PFN(offset);
return memblock_is_map_memory(pfn);
}

40
arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
View File

@ -11,26 +11,6 @@
compatible = "operating-points-v2";
opp-shared;
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <731000>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <731000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <731000>;
};
opp-667000000 {
opp-hz = /bits/ 64 <667000000>;
opp-microvolt = <731000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <761000>;
@ -71,26 +51,6 @@
compatible = "operating-points-v2";
opp-shared;
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <731000>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <731000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <731000>;
};
opp-667000000 {
opp-hz = /bits/ 64 <667000000>;
opp-microvolt = <731000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <731000>;

40
arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
View File

@ -11,26 +11,6 @@
compatible = "operating-points-v2";
opp-shared;
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <731000>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <731000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <731000>;
};
opp-667000000 {
opp-hz = /bits/ 64 <667000000>;
opp-microvolt = <731000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <731000>;
@ -76,26 +56,6 @@
compatible = "operating-points-v2";
opp-shared;
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <751000>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <751000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <751000>;
};
opp-667000000 {
opp-hz = /bits/ 64 <667000000>;
opp-microvolt = <751000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <771000>;

8
arch/arm64/boot/dts/amlogic/meson-s4.dtsi
View File

@ -13,28 +13,28 @@
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35","arm,armv8";
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35","arm,armv8";
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a35","arm,armv8";
compatible = "arm,cortex-a35";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a35","arm,armv8";
compatible = "arm,cortex-a35";
reg = <0x0 0x3>;
enable-method = "psci";
};

1
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts
View File

@ -437,6 +437,7 @@
"",
"eMMC_RST#", /* BOOT_12 */
"eMMC_DS", /* BOOT_13 */
"", "",
/* GPIOC */
"SD_D0_B", /* GPIOC_0 */
"SD_D1_B", /* GPIOC_1 */

20
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
View File

@ -95,26 +95,6 @@
compatible = "operating-points-v2";
opp-shared;
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-microvolt = <730000>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <730000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <730000>;
};
opp-667000000 {
opp-hz = /bits/ 64 <666666666>;
opp-microvolt = <750000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <770000>;

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View File

@ -146,12 +146,14 @@
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
@ -215,7 +217,7 @@
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
View File

@ -211,12 +211,14 @@
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
@ -309,7 +311,7 @@
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
View File

@ -238,12 +238,14 @@
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
@ -358,7 +360,7 @@
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};

4
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
View File

@ -59,6 +59,10 @@
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";

10
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -293,7 +293,7 @@
ranges;
sai2: sai@30020000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30020000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
@ -307,7 +307,7 @@
};
sai3: sai@30030000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30030000 0x10000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
@ -321,7 +321,7 @@
};
sai5: sai@30050000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30050000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
@ -337,7 +337,7 @@
};
sai6: sai@30060000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x30060000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
@ -394,7 +394,7 @@
};
sai7: sai@300b0000 {
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
reg = <0x300b0000 0x10000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SAI7_IPG>,

2
arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi
View File

@ -253,7 +253,7 @@
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <84000000>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};

2
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View File

@ -196,7 +196,7 @@
};
clk: clock-controller {
compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
#clock-cells = <2>;
};

8
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
View File

@ -262,25 +262,25 @@
gpio4 {
pins = "gpio4";
function = "32k-out1";
drive-push-pull;
drive-push-pull = <1>;
};
gpio5 {
pins = "gpio5";
function = "gpio";
drive-push-pull;
drive-push-pull = <0>;
};
gpio6 {
pins = "gpio6";
function = "gpio";
drive-push-pull;
drive-push-pull = <1>;
};
gpio7 {
pins = "gpio7";
function = "gpio";
drive-push-pull;
drive-push-pull = <0>;
};
};

8
arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts
View File

@ -462,25 +462,25 @@
gpio4 {
pins = "gpio4";
function = "32k-out1";
drive-push-pull;
drive-push-pull = <1>;
};
gpio5 {
pins = "gpio5";
function = "gpio";
drive-push-pull;
drive-push-pull = <0>;
};
gpio6 {
pins = "gpio6";
function = "gpio";
drive-push-pull;
drive-push-pull = <1>;
};
gpio7 {
pins = "gpio7";
function = "gpio";
drive-push-pull;
drive-push-pull = <1>;
};
};

6
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
View File

@ -174,19 +174,19 @@
gpio4 {
pins = "gpio4";
function = "32k-out1";
drive-push-pull;
drive-push-pull = <1>;
};
gpio6 {
pins = "gpio6";
function = "gpio";
drive-push-pull;
drive-push-pull = <1>;
};
gpio7 {
pins = "gpio7";
function = "gpio";
drive-push-pull;
drive-push-pull = <0>;
};
};

6
arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi
View File

@ -148,19 +148,19 @@
gpio4 {
pins = "gpio4";
function = "32k-out1";
drive-push-pull;
drive-push-pull = <1>;
};
gpio6 {
pins = "gpio6";
function = "gpio";
drive-push-pull;
drive-push-pull = <1>;
};
gpio7 {
pins = "gpio7";
function = "gpio";
drive-push-pull;
drive-push-pull = <0>;
};
};

6
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
View File

@ -59,7 +59,7 @@
gpio1 {
pins = "gpio1";
function = "fps-out";
drive-push-pull;
drive-push-pull = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <7>;
maxim,active-fps-power-down-slot = <0>;
@ -68,7 +68,7 @@
gpio2_3 {
pins = "gpio2", "gpio3";
function = "fps-out";
drive-open-drain;
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
@ -80,7 +80,7 @@
gpio5_6_7 {
pins = "gpio5", "gpio6", "gpio7";
function = "gpio";
drive-push-pull;
drive-push-pull = <1>;
};
};

8
arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi
View File

@ -1351,7 +1351,7 @@
gpio1 {
pins = "gpio1";
function = "fps-out";
drive-push-pull;
drive-push-pull = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <7>;
maxim,active-fps-power-down-slot = <0>;
@ -1360,14 +1360,14 @@
gpio2 {
pins = "gpio2";
function = "fps-out";
drive-open-drain;
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
gpio3 {
pins = "gpio3";
function = "fps-out";
drive-open-drain;
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
@ -1379,7 +1379,7 @@
gpio5_6_7 {
pins = "gpio5", "gpio6", "gpio7";
function = "gpio";
drive-push-pull;
drive-push-pull = <1>;
};
};

8
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
View File

@ -195,7 +195,7 @@
gpio1 {
pins = "gpio1";
function = "fps-out";
drive-push-pull;
drive-push-pull = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
maxim,active-fps-power-up-slot = <0>;
maxim,active-fps-power-down-slot = <7>;
@ -204,7 +204,7 @@
gpio2 {
pins = "gpio2";
function = "fps-out";
drive-open-drain;
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <0>;
maxim,active-fps-power-down-slot = <7>;
@ -213,7 +213,7 @@
gpio3 {
pins = "gpio3";
function = "fps-out";
drive-open-drain;
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <4>;
maxim,active-fps-power-down-slot = <3>;
@ -227,7 +227,7 @@
gpio5_6_7 {
pins = "gpio5", "gpio6", "gpio7";
function = "gpio";
drive-push-pull;
drive-push-pull = <1>;
};
};

4
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
View File

@ -1386,7 +1386,7 @@
gpio3 {
pins = "gpio3";
function = "fps-out";
drive-open-drain;
drive-open-drain = <1>;
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
maxim,active-fps-power-up-slot = <4>;
maxim,active-fps-power-down-slot = <2>;
@ -1395,7 +1395,7 @@
gpio5_6 {
pins = "gpio5", "gpio6";
function = "gpio";
drive-push-pull;
drive-push-pull = <1>;
};
gpio4 {

4
arch/arm64/include/asm/io.h
View File

@ -192,4 +192,8 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
unsigned long flags);
#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
#endif /* __ASM_IO_H */

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