ASoC: mediatek: mt8188-mt6359: Use bitfield macros for registers
Replace open coded instances of FIELD_GET() with it, move register definitions at the top of the file and also replace magic numbers with register definitions. While at it, also change a regmap_update_bits() call to regmap_write() because the top 29 bits of AUD_TOP_CFG (31:3) are reserved (unused). Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230608084727.74403-6-angelogioacchino.delregno@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -6,6 +6,7 @@
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* Author: Trevor Wu <trevor.wu@mediatek.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/input.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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@ -19,6 +20,15 @@
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#include "../common/mtk-afe-platform-driver.h"
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#include "../common/mtk-soundcard-driver.h"
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#define CKSYS_AUD_TOP_CFG 0x032c
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#define RG_TEST_ON BIT(0)
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#define RG_TEST_TYPE BIT(2)
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#define CKSYS_AUD_TOP_MON 0x0330
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#define TEST_MISO_COUNT_1 GENMASK(3, 0)
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#define TEST_MISO_COUNT_2 GENMASK(7, 4)
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#define TEST_MISO_DONE_1 BIT(28)
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#define TEST_MISO_DONE_2 BIT(29)
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#define NAU8825_HS_PRESENT BIT(0)
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/*
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@ -251,9 +261,6 @@ static const struct snd_kcontrol_new mt8188_nau8825_controls[] = {
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SOC_DAPM_PIN_SWITCH("Headphone Jack"),
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};
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#define CKSYS_AUD_TOP_CFG 0x032c
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#define CKSYS_AUD_TOP_MON 0x0330
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static int mt8188_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
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{
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struct snd_soc_component *cmpnt_afe =
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@ -265,13 +272,13 @@ static int mt8188_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
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struct mtkaif_param *param;
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int chosen_phase_1, chosen_phase_2;
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int prev_cycle_1, prev_cycle_2;
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int test_done_1, test_done_2;
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u8 test_done_1, test_done_2;
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int cycle_1, cycle_2;
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int mtkaif_chosen_phase[MT8188_MTKAIF_MISO_NUM];
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int mtkaif_phase_cycle[MT8188_MTKAIF_MISO_NUM];
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int mtkaif_calibration_num_phase;
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bool mtkaif_calibration_ok;
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unsigned int monitor = 0;
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u32 monitor = 0;
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int counter;
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int phase;
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int i;
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@ -303,8 +310,7 @@ static int mt8188_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
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mt6359_mtkaif_calibration_enable(cmpnt_codec);
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/* set test type to synchronizer pulse */
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regmap_update_bits(afe_priv->topckgen,
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CKSYS_AUD_TOP_CFG, 0xffff, 0x4);
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regmap_write(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, RG_TEST_TYPE);
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mtkaif_calibration_num_phase = 42; /* mt6359: 0 ~ 42 */
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mtkaif_calibration_ok = true;
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@ -314,7 +320,7 @@ static int mt8188_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
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mt6359_set_mtkaif_calibration_phase(cmpnt_codec,
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phase, phase, phase);
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regmap_set_bits(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, 0x1);
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regmap_set_bits(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, RG_TEST_ON);
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test_done_1 = 0;
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test_done_2 = 0;
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@ -326,14 +332,14 @@ static int mt8188_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
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while (!(test_done_1 & test_done_2)) {
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regmap_read(afe_priv->topckgen,
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CKSYS_AUD_TOP_MON, &monitor);
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test_done_1 = (monitor >> 28) & 0x1;
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test_done_2 = (monitor >> 29) & 0x1;
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test_done_1 = FIELD_GET(TEST_MISO_DONE_1, monitor);
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test_done_2 = FIELD_GET(TEST_MISO_DONE_2, monitor);
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if (test_done_1 == 1)
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cycle_1 = monitor & 0xf;
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cycle_1 = FIELD_GET(TEST_MISO_COUNT_1, monitor);
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if (test_done_2 == 1)
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cycle_2 = (monitor >> 4) & 0xf;
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cycle_2 = FIELD_GET(TEST_MISO_COUNT_2, monitor);
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/* handle if never test done */
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if (++counter > 10000) {
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@ -361,7 +367,7 @@ static int mt8188_mt6359_mtkaif_calibration(struct snd_soc_pcm_runtime *rtd)
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mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1] = prev_cycle_2;
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}
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regmap_clear_bits(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, 0x1);
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regmap_clear_bits(afe_priv->topckgen, CKSYS_AUD_TOP_CFG, RG_TEST_ON);
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if (mtkaif_chosen_phase[MT8188_MTKAIF_MISO_0] >= 0 &&
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mtkaif_chosen_phase[MT8188_MTKAIF_MISO_1] >= 0)
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