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drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.

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For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
The Guest should not program CP_INT_CNTL_RING0 again.

Signed-off-by: Gavin Wan <Gavin.Wan@amd.com>
Reviewed-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Gavin Wan 2020-05-21 19:35:28 +00:00 committed by Alex Deucher
parent 49d2a388bf
commit b0f8a6d5ef
1 changed files with 6 additions and 1 deletions
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7
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
u32 tmp;
if (amdgpu_sriov_vf(adev))
return;
tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
enable ? 1 : 0);