dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema
Restruct i.MX PCIe schema, derive the common properties, thus they can be shared by both the RC and Endpoint schema. Update the description of fsl,imx6q-pcie.yaml, and move the EP mode compatible to fsl,imx6q-pcie-ep.yaml. Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER accordingly. Link: https://lore.kernel.org/r/1676441915-1394-2-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Richard Zhu
Lorenzo Pieralisi
parent
b80b848bdf
commit
b10f82380e
279
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
Normal file
279
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
Normal file
@ -0,0 +1,279 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX6 PCIe RC/EP controller
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maintainers:
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- Lucas Stach <l.stach@pengutronix.de>
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- Richard Zhu <hongxing.zhu@nxp.com>
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description:
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Generic Freescale i.MX PCIe Root Port and Endpoint controller
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properties.
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properties:
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clocks:
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minItems: 3
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items:
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- description: PCIe bridge clock.
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- description: PCIe bus clock.
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- description: PCIe PHY clock.
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- description: Additional required clock entry for imx6sx-pcie,
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imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
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clock-names:
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minItems: 3
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items:
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- const: pcie
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- const: pcie_bus
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- enum: [ pcie_phy, pcie_aux ]
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- enum: [ pcie_inbound_axi, pcie_aux ]
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num-lanes:
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const: 1
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fsl,imx7d-pcie-phy:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to an fsl,imx7d-pcie-phy node. Additional
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required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,
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and imx8mq-pcie-ep.
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power-domains:
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minItems: 1
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items:
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- description: The phandle pointing to the DISPLAY domain for
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imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for
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imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.
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- description: The phandle pointing to the PCIE_PHY power domains
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for imx6sx-pcie and imx6sx-pcie-ep.
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power-domain-names:
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minItems: 1
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items:
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- const: pcie
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- const: pcie_phy
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resets:
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minItems: 2
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maxItems: 3
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description: Phandles to PCIe-related reset lines exposed by SRC
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IP block. Additional required by imx7d-pcie, imx7d-pcie-ep,
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imx8mq-pcie, and imx8mq-pcie-ep.
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reset-names:
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minItems: 2
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maxItems: 3
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fsl,tx-deemph-gen1:
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description: Gen1 De-emphasis value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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fsl,tx-deemph-gen2-3p5db:
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description: Gen2 (3.5db) De-emphasis value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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fsl,tx-deemph-gen2-6db:
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description: Gen2 (6db) De-emphasis value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 20
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fsl,tx-swing-full:
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description: Gen2 TX SWING FULL value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 127
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fsl,tx-swing-low:
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description: TX launch amplitude swing_low value (optional required).
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 127
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fsl,max-link-speed:
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description: Specify PCI Gen for link capability (optional required).
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Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
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requirements and thus for gen2 capability a gen2 compliant clock
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generator should be used and configured.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 2, 3, 4]
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default: 1
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phys:
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maxItems: 1
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phy-names:
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const: pcie-phy
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vpcie-supply:
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description: Should specify the regulator in charge of PCIe port power.
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The regulator will be enabled when initializing the PCIe host and
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disabled either as part of the init process or when shutting down
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the host (optional required).
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vph-supply:
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description: Should specify the regulator in charge of VPH one of
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the three PCIe PHY powers. This regulator can be supplied by both
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1.8v and 3.3v voltage supplies (optional required).
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required:
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- clocks
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- clock-names
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- num-lanes
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6sx-pcie
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- fsl,imx6sx-pcie-ep
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then:
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properties:
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clock-names:
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items:
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- {}
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- {}
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- const: pcie_phy
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- const: pcie_inbound_axi
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power-domains:
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minItems: 2
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power-domain-names:
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minItems: 2
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8mq-pcie
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- fsl,imx8mq-pcie-ep
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then:
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properties:
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clock-names:
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items:
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- {}
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- {}
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- const: pcie_phy
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- const: pcie_aux
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- if:
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properties:
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compatible:
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not:
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contains:
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enum:
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- fsl,imx6sx-pcie
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- fsl,imx8mq-pcie
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- fsl,imx6sx-pcie-ep
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- fsl,imx8mq-pcie-ep
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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maxItems: 3
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6qp-pcie
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- fsl,imx7d-pcie
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- fsl,imx6q-pcie-ep
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- fsl,imx6qp-pcie-ep
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- fsl,imx7d-pcie-ep
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then:
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properties:
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clock-names:
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maxItems: 3
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contains:
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const: pcie_phy
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8mm-pcie
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- fsl,imx8mp-pcie
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- fsl,imx8mm-pcie-ep
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- fsl,imx8mp-pcie-ep
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then:
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properties:
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clock-names:
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maxItems: 3
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contains:
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const: pcie_aux
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6qp-pcie
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- fsl,imx6q-pcie-ep
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- fsl,imx6qp-pcie-ep
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then:
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properties:
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power-domains: false
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power-domain-names: false
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6sx-pcie
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- fsl,imx6q-pcie
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- fsl,imx6qp-pcie
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- fsl,imx6sx-pcie-ep
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- fsl,imx6q-pcie-ep
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- fsl,imx6qp-pcie-ep
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then:
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properties:
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power-domains:
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maxItems: 1
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power-domain-names: false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6sx-pcie
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- fsl,imx6qp-pcie
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- fsl,imx7d-pcie
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- fsl,imx8mq-pcie
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- fsl,imx6q-pcie-ep
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- fsl,imx6sx-pcie-ep
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- fsl,imx6qp-pcie-ep
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- fsl,imx7d-pcie-ep
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- fsl,imx8mq-pcie-ep
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then:
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properties:
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resets:
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minItems: 3
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reset-names:
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items:
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- const: pciephy
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- const: apps
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- const: turnoff
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else:
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properties:
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: apps
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- const: turnoff
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additionalProperties: true
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...
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85
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
Normal file
85
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
Normal file
@ -0,0 +1,85 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX6 PCIe Endpoint controller
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maintainers:
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- Lucas Stach <l.stach@pengutronix.de>
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- Richard Zhu <hongxing.zhu@nxp.com>
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description: |+
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This PCIe controller is based on the Synopsys DesignWare PCIe IP and
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thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
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The controller instances are dual mode where in they can work either in
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Root Port mode or Endpoint mode but one at a time.
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properties:
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compatible:
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enum:
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- fsl,imx8mm-pcie-ep
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- fsl,imx8mq-pcie-ep
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- fsl,imx8mp-pcie-ep
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reg:
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minItems: 2
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reg-names:
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items:
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- const: dbi
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- const: addr_space
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interrupts:
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items:
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- description: builtin eDMA interrupter.
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interrupt-names:
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items:
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- const: dma
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/power/imx8mp-power.h>
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#include <dt-bindings/reset/imx8mp-reset.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie_ep: pcie-ep@33800000 {
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compatible = "fsl,imx8mp-pcie-ep";
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reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
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reg-names = "dbi", "addr_space";
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clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
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<&clk IMX8MP_CLK_HSIO_AXI>,
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<&clk IMX8MP_CLK_PCIE_ROOT>;
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clock-names = "pcie", "pcie_bus", "pcie_aux";
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assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
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assigned-clock-rates = <10000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
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num-lanes = <1>;
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
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interrupt-names = "dma";
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fsl,max-link-speed = <3>;
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power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
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resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
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<&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
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reset-names = "apps", "turnoff";
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
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num-ib-windows = <4>;
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num-ob-windows = <4>;
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};
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@ -13,6 +13,11 @@ maintainers:
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description: |+
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in snps,dw-pcie.yaml.
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The controller instances are dual mode where in they can work either in
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Root Port mode or Endpoint mode but one at a time.
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See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
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bindings.
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properties:
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compatible:
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@ -24,9 +29,6 @@ properties:
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- fsl,imx8mq-pcie
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- fsl,imx8mm-pcie
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- fsl,imx8mp-pcie
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- fsl,imx8mm-pcie-ep
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- fsl,imx8mq-pcie-ep
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- fsl,imx8mp-pcie-ep
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reg:
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items:
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@ -46,96 +48,6 @@ properties:
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items:
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- const: msi
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clocks:
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minItems: 3
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items:
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- description: PCIe bridge clock.
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- description: PCIe bus clock.
|
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- description: PCIe PHY clock.
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- description: Additional required clock entry for imx6sx-pcie,
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imx8mq-pcie.
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clock-names:
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minItems: 3
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items:
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- const: pcie
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- const: pcie_bus
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- enum: [ pcie_phy, pcie_aux ]
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- enum: [ pcie_inbound_axi, pcie_aux ]
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num-lanes:
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const: 1
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fsl,imx7d-pcie-phy:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to an fsl,imx7d-pcie-phy node. Additional
|
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required properties for imx7d-pcie and imx8mq-pcie.
|
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|
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power-domains:
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minItems: 1
|
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items:
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- description: The phandle pointing to the DISPLAY domain for
|
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imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
|
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imx8mq-pcie.
|
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- description: The phandle pointing to the PCIE_PHY power domains
|
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for imx6sx-pcie.
|
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power-domain-names:
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minItems: 1
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items:
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- const: pcie
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- const: pcie_phy
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resets:
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minItems: 2
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maxItems: 3
|
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description: Phandles to PCIe-related reset lines exposed by SRC
|
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IP block. Additional required by imx7d-pcie and imx8mq-pcie.
|
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|
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reset-names:
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minItems: 2
|
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maxItems: 3
|
||||
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fsl,tx-deemph-gen1:
|
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description: Gen1 De-emphasis value (optional required).
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||||
$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
|
||||
|
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fsl,tx-deemph-gen2-3p5db:
|
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description: Gen2 (3.5db) De-emphasis value (optional required).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
|
||||
fsl,tx-deemph-gen2-6db:
|
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description: Gen2 (6db) De-emphasis value (optional required).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 20
|
||||
|
||||
fsl,tx-swing-full:
|
||||
description: Gen2 TX SWING FULL value (optional required).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 127
|
||||
|
||||
fsl,tx-swing-low:
|
||||
description: TX launch amplitude swing_low value (optional required).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 127
|
||||
|
||||
fsl,max-link-speed:
|
||||
description: Specify PCI Gen for link capability (optional required).
|
||||
Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
|
||||
requirements and thus for gen2 capability a gen2 compliant clock
|
||||
generator should be used and configured.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 2, 3, 4]
|
||||
default: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: pcie-phy
|
||||
|
||||
reset-gpio:
|
||||
description: Should specify the GPIO for controlling the PCI bus device
|
||||
reset signal. It's not polarity aware and defaults to active-low reset
|
||||
@ -147,17 +59,6 @@ properties:
|
||||
L=operation state) (optional required).
|
||||
type: boolean
|
||||
|
||||
vpcie-supply:
|
||||
description: Should specify the regulator in charge of PCIe port power.
|
||||
The regulator will be enabled when initializing the PCIe host and
|
||||
disabled either as part of the init process or when shutting down
|
||||
the host (optional required).
|
||||
|
||||
vph-supply:
|
||||
description: Should specify the regulator in charge of VPH one of
|
||||
the three PCIe PHY powers. This regulator can be supplied by both
|
||||
1.8v and 3.3v voltage supplies (optional required).
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -167,144 +68,15 @@ required:
|
||||
- device_type
|
||||
- bus-range
|
||||
- ranges
|
||||
- num-lanes
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,imx6sx-pcie
|
||||
then:
|
||||
properties:
|
||||
clock-names:
|
||||
items:
|
||||
- {}
|
||||
- {}
|
||||
- const: pcie_phy
|
||||
- const: pcie_inbound_axi
|
||||
power-domains:
|
||||
minItems: 2
|
||||
power-domain-names:
|
||||
minItems: 2
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,imx8mq-pcie
|
||||
then:
|
||||
properties:
|
||||
clock-names:
|
||||
items:
|
||||
- {}
|
||||
- {}
|
||||
- const: pcie_phy
|
||||
- const: pcie_aux
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
not:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx6sx-pcie
|
||||
- fsl,imx8mq-pcie
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
maxItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx6q-pcie
|
||||
- fsl,imx6qp-pcie
|
||||
- fsl,imx7d-pcie
|
||||
then:
|
||||
properties:
|
||||
clock-names:
|
||||
maxItems: 3
|
||||
contains:
|
||||
const: pcie_phy
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx8mm-pcie
|
||||
- fsl,imx8mp-pcie
|
||||
then:
|
||||
properties:
|
||||
clock-names:
|
||||
maxItems: 3
|
||||
contains:
|
||||
const: pcie_aux
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx6q-pcie
|
||||
- fsl,imx6qp-pcie
|
||||
then:
|
||||
properties:
|
||||
power-domains: false
|
||||
power-domain-names: false
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx6sx-pcie
|
||||
- fsl,imx6q-pcie
|
||||
- fsl,imx6qp-pcie
|
||||
then:
|
||||
properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
power-domain-names: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx6q-pcie
|
||||
- fsl,imx6sx-pcie
|
||||
- fsl,imx6qp-pcie
|
||||
- fsl,imx7d-pcie
|
||||
- fsl,imx8mq-pcie
|
||||
then:
|
||||
properties:
|
||||
resets:
|
||||
minItems: 3
|
||||
reset-names:
|
||||
items:
|
||||
- const: pciephy
|
||||
- const: apps
|
||||
- const: turnoff
|
||||
else:
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 2
|
||||
reset-names:
|
||||
items:
|
||||
- const: apps
|
||||
- const: turnoff
|
||||
- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@ -15973,6 +15973,8 @@ M: Lucas Stach <l.stach@pengutronix.de>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
|
||||
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
|
||||
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
|
||||
F: drivers/pci/controller/dwc/*imx6*
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user