drm/amdgpu: add helpers for hdp ras init/fini
hdp ras init/fini are common functions that can be shared among hdp generations Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -56,7 +56,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
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amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
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amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
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amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
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amdgpu_fw_attestation.o amdgpu_securedisplay.o
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amdgpu_fw_attestation.o amdgpu_securedisplay.o amdgpu_hdp.o
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amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
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69
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
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69
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
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@ -0,0 +1,69 @@
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev)
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{
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int r;
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struct ras_ih_if ih_info = {
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.cb = NULL,
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};
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struct ras_fs_if fs_info = {
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.sysfs_name = "hdp_err_count",
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};
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if (!adev->hdp.ras_if) {
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adev->hdp.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
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if (!adev->hdp.ras_if)
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return -ENOMEM;
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adev->hdp.ras_if->block = AMDGPU_RAS_BLOCK__HDP;
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adev->hdp.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->hdp.ras_if->sub_block_index = 0;
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strcpy(adev->hdp.ras_if->name, "hdp");
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}
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ih_info.head = fs_info.head = *adev->hdp.ras_if;
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r = amdgpu_ras_late_init(adev, adev->hdp.ras_if,
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&fs_info, &ih_info);
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if (r || !amdgpu_ras_is_supported(adev, adev->hdp.ras_if->block)) {
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kfree(adev->hdp.ras_if);
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adev->hdp.ras_if = NULL;
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}
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return r;
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}
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void amdgpu_hdp_ras_fini(struct amdgpu_device *adev)
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{
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if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP) &&
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adev->hdp.ras_if) {
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struct ras_common_if *ras_if = adev->hdp.ras_if;
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struct ras_ih_if ih_info = {
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.cb = NULL,
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};
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amdgpu_ras_late_fini(adev, ras_if, &ih_info);
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kfree(ras_if);
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}
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}
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@ -47,4 +47,6 @@ struct amdgpu_hdp {
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const struct amdgpu_hdp_ras_funcs *ras_funcs;
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};
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int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev);
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void amdgpu_hdp_ras_fini(struct amdgpu_device *adev);
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#endif /* __AMDGPU_HDP_H__ */
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