serial: 8250_pci: add support for Intel BayTrail
Intel BayTrail has two HS-UARTs with 64 byte fifo, support for DMA and support for 16750 compatible Auto Flow Control. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Heikki Krogerus
Greg Kroah-Hartman
parent
3415097ff0
commit
b15e5691cc
@ -1324,6 +1324,120 @@ ce4100_serial_setup(struct serial_private *priv,
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return ret;
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}
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#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
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#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
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#define BYT_PRV_CLK 0x800
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#define BYT_PRV_CLK_EN (1 << 0)
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#define BYT_PRV_CLK_M_VAL_SHIFT 1
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#define BYT_PRV_CLK_N_VAL_SHIFT 16
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#define BYT_PRV_CLK_UPDATE (1 << 31)
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#define BYT_GENERAL_REG 0x808
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#define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3)
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#define BYT_TX_OVF_INT 0x820
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#define BYT_TX_OVF_INT_MASK (1 << 1)
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static void
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byt_set_termios(struct uart_port *p, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud = tty_termios_baud_rate(termios);
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unsigned int m = 6912;
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unsigned int n = 15625;
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u32 reg;
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/* For baud rates 1M, 2M, 3M and 4M the dividers must be adjusted. */
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if (baud == 1000000 || baud == 2000000 || baud == 4000000) {
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m = 64;
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n = 100;
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p->uartclk = 64000000;
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} else if (baud == 3000000) {
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m = 48;
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n = 100;
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p->uartclk = 48000000;
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} else {
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p->uartclk = 44236800;
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}
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/* Reset the clock */
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reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
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writel(reg, p->membase + BYT_PRV_CLK);
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reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
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writel(reg, p->membase + BYT_PRV_CLK);
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/*
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* If auto-handshake mechanism is not enabled,
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* disable rts_n override
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*/
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reg = readl(p->membase + BYT_GENERAL_REG);
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reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
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if (termios->c_cflag & CRTSCTS)
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reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
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writel(reg, p->membase + BYT_GENERAL_REG);
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serial8250_do_set_termios(p, termios, old);
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}
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static bool byt_dma_filter(struct dma_chan *chan, void *param)
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{
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return chan->chan_id == *(int *)param;
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}
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static int
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byt_serial_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx)
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{
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struct uart_8250_dma *dma;
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int ret;
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dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL);
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if (!dma)
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return -ENOMEM;
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switch (priv->dev->device) {
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case PCI_DEVICE_ID_INTEL_BYT_UART1:
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dma->rx_chan_id = 3;
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dma->tx_chan_id = 2;
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break;
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case PCI_DEVICE_ID_INTEL_BYT_UART2:
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dma->rx_chan_id = 5;
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dma->tx_chan_id = 4;
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break;
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default:
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return -EINVAL;
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}
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dma->rxconf.slave_id = dma->rx_chan_id;
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dma->rxconf.src_maxburst = 16;
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dma->txconf.slave_id = dma->tx_chan_id;
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dma->txconf.dst_maxburst = 16;
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dma->fn = byt_dma_filter;
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dma->rx_param = &dma->rx_chan_id;
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dma->tx_param = &dma->tx_chan_id;
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ret = pci_default_setup(priv, board, port, idx);
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port->port.iotype = UPIO_MEM;
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port->port.type = PORT_16550A;
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port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
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port->port.set_termios = byt_set_termios;
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port->port.fifosize = 64;
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port->tx_loadsz = 64;
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port->dma = dma;
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port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
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/* Disable Tx counter interrupts */
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writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
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return ret;
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}
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static int
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pci_omegapci_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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@ -1662,6 +1776,20 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
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.subdevice = PCI_ANY_ID,
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.setup = kt_serial_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_BYT_UART1,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = byt_serial_setup,
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},
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{
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_BYT_UART2,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.setup = byt_serial_setup,
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},
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/*
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* ITE
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*/
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@ -2449,6 +2577,7 @@ enum pci_board_num_t {
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pbn_ADDIDATA_PCIe_4_3906250,
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pbn_ADDIDATA_PCIe_8_3906250,
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pbn_ce4100_1_115200,
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pbn_byt,
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pbn_omegapci,
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pbn_NETMOS9900_2s_115200,
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pbn_brcm_trumanage,
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@ -3185,6 +3314,13 @@ static struct pciserial_board pci_boards[] = {
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.base_baud = 921600,
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.reg_shift = 2,
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},
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[pbn_byt] = {
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.flags = FL_BASE0,
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.num_ports = 1,
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.base_baud = 2764800,
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.uart_offset = 0x80,
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.reg_shift = 2,
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},
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[pbn_omegapci] = {
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.flags = FL_BASE0,
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.num_ports = 8,
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@ -4846,6 +4982,15 @@ static struct pci_device_id serial_pci_tbl[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_ce4100_1_115200 },
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/* Intel BayTrail */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
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PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
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pbn_byt },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
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PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
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pbn_byt },
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/*
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* Cronyx Omega PCI
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