gpio updates for v5.9
- use kobj_to_dev() in sysfs interface - kerneldoc and documentation fixes - relax the interrupt flags in gpio-mpc8xxx - support new model in gpio-pca953x - remove a redundant check from gpio-max732x - support a new platform in gpio-zynq (+ some minor fixes) - don't depend on GPIOLIB when already inside the "if GPIOLIB" in Kconfig - support PM ops for suspend in gpio-omap - minor tweaks in gpiolib -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAl77GHcACgkQEacuoBRx 13JBIQ/+PEo8o7hVqpXETQ3NYwoPC4Hov0sE3Ig/ecoAEmTG2FPXU/qcACiO4z64 n9bXadS8iTPBHpblmbTx5MwzWk081GwSR+y3P8mxZUjO6FdVt8v/TZnkgMaat0cv xIM18MbBYzmlwNvpqaIHn7ZlC20mGHeFEBM600QIBkf5+fN0gCZF8cB62jqVZp2e rg1dzmdd7GWMXVIZ+D+XAdPuRsSDNBeGoQG/Ip4sio4VsU64FoSu279V3WGHFbHu 2yfz4QxXOblhXRxT9swMtuPYAON8aai23YlcEDpt6K/j2TJtVibJRlRBDUQAYmNH K2XA7phKcEVCN47rG8XR9v2l5Qkf49eVCOS2Y0f6G+GL9KwezD2WZL/4d+Nyx7CZ YDSIM+ti0FHUb7b6wSFQHJbdKk2sdtqpYaakirNmRAPKPBT+rzyRaNx6XLu2/wMi CVC+LCdxdlsHpnPVcCTjNeGHmZrloDJiQb0A0kpZnPagHXrQaI5tw7OKDKoPi+DA bkYxW++Iq96QRjEvExu0V/3gRNWPjXpWd+sfMJ6b/Lb4orbmlnJcjgVDXDQvqj0N Oga87Mgg5U/pfPYvLvuxwwpMwp1QZv9ex8dG91M62V0Ta+Ja4nOdtpIERHEKKP6d ehKBXzU7F6tREIG3EU+DMm33RWRnM/DYrg7RnPgIHzxDB6Wj18c= =TwKk -----END PGP SIGNATURE----- Merge tag 'gpio-updates-for-v5.9-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel gpio updates for v5.9 - use kobj_to_dev() in sysfs interface - kerneldoc and documentation fixes - relax the interrupt flags in gpio-mpc8xxx - support new model in gpio-pca953x - remove a redundant check from gpio-max732x - support a new platform in gpio-zynq (+ some minor fixes) - don't depend on GPIOLIB when already inside the "if GPIOLIB" in Kconfig - support PM ops for suspend in gpio-omap - minor tweaks in gpiolib
This commit is contained in:
Linus Walleij
commit
b239e4454e
@ -19,6 +19,7 @@ Required properties:
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nxp,pca9698
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nxp,pcal6416
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nxp,pcal6524
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nxp,pcal9535
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nxp,pcal9555a
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maxim,max7310
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maxim,max7312
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@ -6,7 +6,9 @@ Required properties:
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- First cell is the GPIO line number
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- Second cell is used to specify optional
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parameters (unused)
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- compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0"
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- compatible : Should be "xlnx,zynq-gpio-1.0" or
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"xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
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or "xlnx,pmc-gpio-1.0
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- clocks : Clock specifier (see clock bindings for details)
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- gpio-controller : Marks the device node as a GPIO controller.
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- interrupts : Interrupt specifier (see interrupt bindings for
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@ -410,7 +410,7 @@ config GPIO_MXS
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config GPIO_OCTEON
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tristate "Cavium OCTEON GPIO"
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depends on GPIOLIB && CAVIUM_OCTEON_SOC
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depends on CAVIUM_OCTEON_SOC
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default y
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help
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Say yes here to support the on-chip GPIO lines on the OCTEON
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@ -1117,7 +1117,7 @@ config GPIO_DLN2
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config HTC_EGPIO
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bool "HTC EGPIO support"
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depends on GPIOLIB && ARM
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depends on ARM
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help
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This driver supports the CPLD egpio chip present on
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several HTC phones. It provides basic support for input
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@ -5,7 +5,7 @@ subsystem.
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GPIO descriptors
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Starting with commit 79a9becda894 the GPIO subsystem embarked on a journey
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to move away from the global GPIO numberspace and toward a decriptor-based
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to move away from the global GPIO numberspace and toward a descriptor-based
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approach. This means that GPIO consumers, drivers and machine descriptions
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ideally have no use or idea of the global GPIO numberspace that has/was
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used in the inception of the GPIO subsystem.
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@ -417,7 +417,7 @@ static int mpc8xxx_probe(struct platform_device *pdev)
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ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
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mpc8xxx_gpio_irq_cascade,
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IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
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IRQF_SHARED, "gpio-cascade",
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mpc8xxx_gc);
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if (ret) {
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dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n",
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@ -60,6 +60,7 @@ struct gpio_bank {
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struct clk *dbck;
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struct notifier_block nb;
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unsigned int is_suspended:1;
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unsigned int needs_resume:1;
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u32 mod_usage;
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u32 irq_usage;
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u32 dbck_enable_mask;
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@ -1504,9 +1505,34 @@ static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
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return 0;
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}
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static int omap_gpio_suspend(struct device *dev)
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{
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struct gpio_bank *bank = dev_get_drvdata(dev);
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if (bank->is_suspended)
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return 0;
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bank->needs_resume = 1;
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return omap_gpio_runtime_suspend(dev);
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}
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static int omap_gpio_resume(struct device *dev)
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{
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struct gpio_bank *bank = dev_get_drvdata(dev);
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if (!bank->needs_resume)
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return 0;
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bank->needs_resume = 0;
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return omap_gpio_runtime_resume(dev);
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}
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static const struct dev_pm_ops gpio_pm_ops = {
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SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
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NULL)
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SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
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};
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static struct platform_driver omap_gpio_driver = {
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@ -89,6 +89,7 @@ static const struct i2c_device_id pca953x_id[] = {
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{ "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
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{ "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
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{ "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
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{ "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
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{ "max7310", 8 | PCA953X_TYPE, },
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@ -1145,6 +1146,7 @@ static const struct of_device_id pca953x_dt_ids[] = {
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{ .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
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{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
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{ .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
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{ .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
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{ .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
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@ -10,6 +10,7 @@
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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@ -21,6 +22,9 @@
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/* Maximum banks */
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#define ZYNQ_GPIO_MAX_BANK 4
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#define ZYNQMP_GPIO_MAX_BANK 6
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#define VERSAL_GPIO_MAX_BANK 4
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#define PMC_GPIO_MAX_BANK 5
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#define VERSAL_UNUSED_BANKS 2
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#define ZYNQ_GPIO_BANK0_NGPIO 32
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#define ZYNQ_GPIO_BANK1_NGPIO 22
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@ -95,6 +99,7 @@
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/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
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#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
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#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
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#define GPIO_QUIRK_VERSAL BIT(2)
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struct gpio_regs {
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u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
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@ -116,6 +121,7 @@ struct gpio_regs {
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* @irq: interrupt for the GPIO device
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* @p_data: pointer to platform data
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* @context: context registers
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* @dirlock: lock used for direction in/out synchronization
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*/
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struct zynq_gpio {
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struct gpio_chip chip;
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@ -124,6 +130,7 @@ struct zynq_gpio {
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int irq;
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const struct zynq_platform_data *p_data;
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struct gpio_regs context;
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spinlock_t dirlock; /* lock */
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};
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/**
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@ -196,6 +203,8 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
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gpio->p_data->bank_min[bank];
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return;
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}
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if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
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bank = bank + VERSAL_UNUSED_BANKS;
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}
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/* default */
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@ -297,6 +306,7 @@ static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
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{
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u32 reg;
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unsigned int bank_num, bank_pin_num;
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unsigned long flags;
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struct zynq_gpio *gpio = gpiochip_get_data(chip);
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zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
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@ -310,9 +320,11 @@ static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
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return -EINVAL;
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/* clear the bit in direction mode reg to set the pin as input */
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spin_lock_irqsave(&gpio->dirlock, flags);
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reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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reg &= ~BIT(bank_pin_num);
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writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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spin_unlock_irqrestore(&gpio->dirlock, flags);
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return 0;
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}
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@ -334,11 +346,13 @@ static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
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{
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u32 reg;
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unsigned int bank_num, bank_pin_num;
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unsigned long flags;
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struct zynq_gpio *gpio = gpiochip_get_data(chip);
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zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
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/* set the GPIO pin as output */
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spin_lock_irqsave(&gpio->dirlock, flags);
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reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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reg |= BIT(bank_pin_num);
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writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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@ -347,6 +361,7 @@ static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
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reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
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reg |= BIT(bank_pin_num);
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writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
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spin_unlock_irqrestore(&gpio->dirlock, flags);
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/* set the state of the pin */
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zynq_gpio_set_value(chip, pin, state);
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@ -647,6 +662,8 @@ static void zynq_gpio_irqhandler(struct irq_desc *desc)
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int_enb = readl_relaxed(gpio->base_addr +
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ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
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zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
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if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
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bank_num = bank_num + VERSAL_UNUSED_BANKS;
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}
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chained_irq_exit(irqchip, desc);
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@ -676,6 +693,8 @@ static void zynq_gpio_save_context(struct zynq_gpio *gpio)
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gpio->context.int_any[bank_num] =
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readl_relaxed(gpio->base_addr +
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ZYNQ_GPIO_INTANY_OFFSET(bank_num));
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if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
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bank_num = bank_num + VERSAL_UNUSED_BANKS;
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}
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}
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@ -707,6 +726,8 @@ static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
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writel_relaxed(~(gpio->context.int_en[bank_num]),
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gpio->base_addr +
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ZYNQ_GPIO_INTEN_OFFSET(bank_num));
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if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
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bank_num = bank_num + VERSAL_UNUSED_BANKS;
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}
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}
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@ -715,6 +736,9 @@ static int __maybe_unused zynq_gpio_suspend(struct device *dev)
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struct zynq_gpio *gpio = dev_get_drvdata(dev);
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struct irq_data *data = irq_get_irq_data(gpio->irq);
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if (!device_may_wakeup(dev))
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disable_irq(gpio->irq);
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if (!irqd_is_wakeup_set(data)) {
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zynq_gpio_save_context(gpio);
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return pm_runtime_force_suspend(dev);
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@ -729,6 +753,9 @@ static int __maybe_unused zynq_gpio_resume(struct device *dev)
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struct irq_data *data = irq_get_irq_data(gpio->irq);
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int ret;
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if (!device_may_wakeup(dev))
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enable_irq(gpio->irq);
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if (!irqd_is_wakeup_set(data)) {
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ret = pm_runtime_force_resume(dev);
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zynq_gpio_restore_context(gpio);
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@ -778,6 +805,31 @@ static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
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zynq_gpio_runtime_resume, NULL)
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};
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static const struct zynq_platform_data versal_gpio_def = {
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.label = "versal_gpio",
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.quirks = GPIO_QUIRK_VERSAL,
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.ngpio = 58,
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.max_bank = VERSAL_GPIO_MAX_BANK,
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.bank_min[0] = 0,
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.bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
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.bank_min[3] = 26,
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.bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
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};
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static const struct zynq_platform_data pmc_gpio_def = {
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.label = "pmc_gpio",
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.ngpio = 116,
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.max_bank = PMC_GPIO_MAX_BANK,
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.bank_min[0] = 0,
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.bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
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.bank_min[1] = 26,
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.bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
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.bank_min[3] = 52,
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.bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
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.bank_min[4] = 84,
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.bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
|
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};
|
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|
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static const struct zynq_platform_data zynqmp_gpio_def = {
|
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.label = "zynqmp_gpio",
|
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.quirks = GPIO_QUIRK_DATA_RO_BUG,
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@ -815,6 +867,8 @@ static const struct zynq_platform_data zynq_gpio_def = {
|
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static const struct of_device_id zynq_gpio_of_match[] = {
|
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{ .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
|
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{ .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
|
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{ .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
|
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{ .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
|
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{ /* end of table */ }
|
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};
|
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MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
|
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@ -876,7 +930,8 @@ static int zynq_gpio_probe(struct platform_device *pdev)
|
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/* Retrieve GPIO clock */
|
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gpio->clk = devm_clk_get(&pdev->dev, NULL);
|
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if (IS_ERR(gpio->clk)) {
|
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dev_err(&pdev->dev, "input clock not found.\n");
|
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if (PTR_ERR(gpio->clk) != -EPROBE_DEFER)
|
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dev_err(&pdev->dev, "input clock not found.\n");
|
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return PTR_ERR(gpio->clk);
|
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}
|
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ret = clk_prepare_enable(gpio->clk);
|
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@ -885,6 +940,8 @@ static int zynq_gpio_probe(struct platform_device *pdev)
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return ret;
|
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}
|
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|
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spin_lock_init(&gpio->dirlock);
|
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|
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pm_runtime_set_active(&pdev->dev);
|
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pm_runtime_enable(&pdev->dev);
|
||||
ret = pm_runtime_get_sync(&pdev->dev);
|
||||
@ -892,9 +949,12 @@ static int zynq_gpio_probe(struct platform_device *pdev)
|
||||
goto err_pm_dis;
|
||||
|
||||
/* disable interrupts for all banks */
|
||||
for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
|
||||
for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
|
||||
writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
|
||||
ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
|
||||
if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
|
||||
bank_num = bank_num + VERSAL_UNUSED_BANKS;
|
||||
}
|
||||
|
||||
/* Set up the GPIO irqchip */
|
||||
girq = &chip->irq;
|
||||
@ -919,6 +979,8 @@ static int zynq_gpio_probe(struct platform_device *pdev)
|
||||
goto err_pm_put;
|
||||
}
|
||||
|
||||
irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
|
||||
device_init_wakeup(&pdev->dev, 1);
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -365,7 +365,7 @@ static DEVICE_ATTR_RW(active_low);
|
||||
static umode_t gpio_is_visible(struct kobject *kobj, struct attribute *attr,
|
||||
int n)
|
||||
{
|
||||
struct device *dev = container_of(kobj, struct device, kobj);
|
||||
struct device *dev = kobj_to_dev(kobj);
|
||||
struct gpiod_data *data = dev_get_drvdata(dev);
|
||||
struct gpio_desc *desc = data->desc;
|
||||
umode_t mode = attr->mode;
|
||||
|
||||
@ -2594,10 +2594,9 @@ int gpiod_get_array_value_complex(bool raw, bool can_sleep,
|
||||
bitmap_xor(value_bitmap, value_bitmap,
|
||||
array_info->invert_mask, array_size);
|
||||
|
||||
if (bitmap_full(array_info->get_mask, array_size))
|
||||
return 0;
|
||||
|
||||
i = find_first_zero_bit(array_info->get_mask, array_size);
|
||||
if (i == array_size)
|
||||
return 0;
|
||||
} else {
|
||||
array_info = NULL;
|
||||
}
|
||||
@ -2878,10 +2877,9 @@ int gpiod_set_array_value_complex(bool raw, bool can_sleep,
|
||||
gpio_chip_set_multiple(array_info->chip, array_info->set_mask,
|
||||
value_bitmap);
|
||||
|
||||
if (bitmap_full(array_info->set_mask, array_size))
|
||||
return 0;
|
||||
|
||||
i = find_first_zero_bit(array_info->set_mask, array_size);
|
||||
if (i == array_size)
|
||||
return 0;
|
||||
} else {
|
||||
array_info = NULL;
|
||||
}
|
||||
|
||||
@ -497,7 +497,7 @@ extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
|
||||
|
||||
/**
|
||||
* gpiochip_add_data() - register a gpio_chip
|
||||
* @chip: the chip to register, with chip->base initialized
|
||||
* @gc: the chip to register, with chip->base initialized
|
||||
* @data: driver-private data associated with this chip
|
||||
*
|
||||
* Context: potentially before irqs will work
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user