drm/radeon: properly handle cg on asics without UVD
Don't try and enable clockgating if the asic doesn't have UVD. Use rdev->has_uvd rather than using local checks. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -5215,14 +5215,12 @@ static void si_enable_mc_ls(struct radeon_device *rdev,
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static void si_init_cg(struct radeon_device *rdev)
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static void si_init_cg(struct radeon_device *rdev)
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{
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{
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bool has_uvd = true;
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si_enable_mgcg(rdev, true);
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si_enable_mgcg(rdev, true);
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si_enable_cgcg(rdev, true);
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si_enable_cgcg(rdev, true);
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/* disable MC LS on Tahiti */
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/* disable MC LS on Tahiti */
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if (rdev->family == CHIP_TAHITI)
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if (rdev->family == CHIP_TAHITI)
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si_enable_mc_ls(rdev, false);
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si_enable_mc_ls(rdev, false);
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if (has_uvd) {
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if (rdev->has_uvd) {
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si_enable_uvd_mgcg(rdev, true);
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si_enable_uvd_mgcg(rdev, true);
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si_init_uvd_internal_cg(rdev);
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si_init_uvd_internal_cg(rdev);
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}
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}
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@ -5230,9 +5228,7 @@ static void si_init_cg(struct radeon_device *rdev)
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static void si_fini_cg(struct radeon_device *rdev)
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static void si_fini_cg(struct radeon_device *rdev)
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{
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{
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bool has_uvd = true;
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if (rdev->has_uvd)
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if (has_uvd)
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si_enable_uvd_mgcg(rdev, false);
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si_enable_uvd_mgcg(rdev, false);
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si_enable_cgcg(rdev, false);
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si_enable_cgcg(rdev, false);
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si_enable_mgcg(rdev, false);
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si_enable_mgcg(rdev, false);
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