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drm/i915: Relocate intel_dp_program_link_training_pattern()

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intel_dp_program_link_training_pattern() clearly belongs in
intel_dp_link_training.c. Make it so.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210318161015.22070-4-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2021-03-18 18:10:11 +02:00
parent 6721af21bd
commit b2ef066198
4 changed files with 36 additions and 37 deletions
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33
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -3386,39 +3386,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
static char dp_training_pattern_name(u8 train_pat)
{
switch (train_pat) {
case DP_TRAINING_PATTERN_1:
case DP_TRAINING_PATTERN_2:
case DP_TRAINING_PATTERN_3:
return '0' + train_pat;
case DP_TRAINING_PATTERN_4:
return '4';
default:
MISSING_CASE(train_pat);
return '?';
}
}
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
u8 dp_train_pat)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
if (train_pat != DP_TRAINING_PATTERN_DISABLE)
drm_dbg_kms(&dev_priv->drm,
"[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
encoder->base.base.id, encoder->base.name,
dp_training_pattern_name(train_pat));
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
}
static void
intel_dp_link_down(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state)

4
drivers/gpu/drm/i915/display/intel_dp.h
View File

@ -87,10 +87,6 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits);
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
u8 dp_train_pat);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
u8 *link_bw, u8 *rate_select);
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);

33
drivers/gpu/drm/i915/display/intel_dp_link_training.c
View File

@ -367,6 +367,39 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
}
static char dp_training_pattern_name(u8 train_pat)
{
switch (train_pat) {
case DP_TRAINING_PATTERN_1:
case DP_TRAINING_PATTERN_2:
case DP_TRAINING_PATTERN_3:
return '0' + train_pat;
case DP_TRAINING_PATTERN_4:
return '4';
default:
MISSING_CASE(train_pat);
return '?';
}
}
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
u8 dp_train_pat)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
if (train_pat != DP_TRAINING_PATTERN_DISABLE)
drm_dbg_kms(&dev_priv->drm,
"[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
encoder->base.base.id, encoder->base.name,
dp_training_pattern_name(train_pat));
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
}
void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy)

3
drivers/gpu/drm/i915/display/intel_dp_link_training.h
View File

@ -17,6 +17,9 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy,
const u8 link_status[DP_LINK_STATUS_SIZE]);
void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
u8 dp_train_pat);
void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
enum drm_dp_phy dp_phy);