irqchip: omap-intc: enable TURBO idle mode
When TURBO bit is set in the INTC_IDLE register, the input synchronizer clock will be autogated based on activity on the INTC. Because this idle mode increases the interrupt latency by 2 clock cycles, we're only enabling it during suspend. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -51,6 +51,9 @@
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#define INTCPS_NR_ILR_REGS 128
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#define INTCPS_NR_ILR_REGS 128
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#define INTCPS_NR_MIR_REGS 3
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#define INTCPS_NR_MIR_REGS 3
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#define INTC_IDLE_FUNCIDLE (1 << 0)
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#define INTC_IDLE_TURBO (1 << 1)
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#define INTC_PROTECTION_ENABLE (1 << 0)
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#define INTC_PROTECTION_ENABLE (1 << 0)
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/*
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/*
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@ -134,12 +137,14 @@ void omap3_intc_prepare_idle(void)
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* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
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* cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
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*/
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*/
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intc_writel(INTC_SYSCONFIG, 0);
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intc_writel(INTC_SYSCONFIG, 0);
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intc_writel(INTC_IDLE, INTC_IDLE_TURBO);
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}
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}
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void omap3_intc_resume_idle(void)
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void omap3_intc_resume_idle(void)
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{
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{
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/* Re-enable autoidle */
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/* Re-enable autoidle */
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intc_writel(INTC_SYSCONFIG, 1);
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intc_writel(INTC_SYSCONFIG, 1);
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intc_writel(INTC_IDLE, 0);
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}
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}
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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/* XXX: FIQ and additional INTC support (only MPU at the moment) */
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