net: dsa: qca8k: Switch to PHYLINK instead of PHYLIB
Update the driver to use the new PHYLINK callbacks, removing the legacy adjust_link callback. Signed-off-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jonathan McDowell
David S. Miller
parent
2b3445e814
commit
b3591c2a36
@ -14,6 +14,7 @@
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#include <linux/of_platform.h>
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#include <linux/if_bridge.h>
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#include <linux/mdio.h>
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#include <linux/phylink.h>
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#include <linux/gpio/consumer.h>
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#include <linux/etherdevice.h>
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@ -418,55 +419,6 @@ qca8k_mib_init(struct qca8k_priv *priv)
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mutex_unlock(&priv->reg_mutex);
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}
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static int
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qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
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{
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u32 reg, val;
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switch (port) {
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case 0:
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reg = QCA8K_REG_PORT0_PAD_CTRL;
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break;
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case 6:
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reg = QCA8K_REG_PORT6_PAD_CTRL;
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break;
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default:
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pr_err("Can't set PAD_CTRL on port %d\n", port);
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return -EINVAL;
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}
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/* Configure a port to be directly connected to an external
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* PHY or MAC.
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*/
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switch (mode) {
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case PHY_INTERFACE_MODE_RGMII:
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/* RGMII mode means no delay so don't enable the delay */
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val = QCA8K_PORT_PAD_RGMII_EN;
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qca8k_write(priv, reg, val);
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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/* RGMII_ID needs internal delay. This is enabled through
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* PORT5_PAD_CTRL for all ports, rather than individual port
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* registers
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*/
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qca8k_write(priv, reg,
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QCA8K_PORT_PAD_RGMII_EN |
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QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
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QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
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qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
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QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
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break;
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default:
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pr_err("xMII mode %d not supported\n", mode);
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return -EINVAL;
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}
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return 0;
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}
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static void
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qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
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{
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@ -639,9 +591,7 @@ static int
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qca8k_setup(struct dsa_switch *ds)
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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phy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;
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int ret, i;
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u32 mask;
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/* Make sure that port 0 is the cpu port */
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if (!dsa_is_cpu_port(ds, 0)) {
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@ -661,24 +611,9 @@ qca8k_setup(struct dsa_switch *ds)
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if (ret)
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return ret;
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/* Initialize CPU port pad mode (xMII type, delays...) */
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ret = of_get_phy_mode(dsa_to_port(ds, QCA8K_CPU_PORT)->dn, &phy_mode);
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if (ret) {
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pr_err("Can't find phy-mode for master device\n");
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return ret;
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}
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ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
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if (ret < 0)
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return ret;
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/* Enable CPU Port, force it to maximum bandwidth and full-duplex */
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mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
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QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
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qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
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/* Enable CPU Port */
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qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
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QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
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qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
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priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
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/* Enable MIB counters */
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qca8k_mib_init(priv);
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@ -693,10 +628,9 @@ qca8k_setup(struct dsa_switch *ds)
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qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
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QCA8K_PORT_LOOKUP_MEMBER, 0);
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/* Disable MAC by default on all user ports */
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/* Disable MAC by default on all ports */
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for (i = 1; i < QCA8K_NUM_PORTS; i++)
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if (dsa_is_user_port(ds, i))
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qca8k_port_set_status(priv, i, 0);
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qca8k_port_set_status(priv, i, 0);
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/* Forward all unknown frames to CPU port for Linux processing */
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qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
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@ -743,44 +677,222 @@ qca8k_setup(struct dsa_switch *ds)
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}
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static void
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qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
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qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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const struct phylink_link_state *state)
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{
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struct qca8k_priv *priv = ds->priv;
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u32 reg;
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/* Force fixed-link setting for CPU port, skip others. */
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if (!phy_is_pseudo_fixed_link(phy))
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return;
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switch (port) {
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case 0: /* 1st CPU port */
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if (state->interface != PHY_INTERFACE_MODE_RGMII &&
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state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
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state->interface != PHY_INTERFACE_MODE_SGMII)
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return;
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/* Set port speed */
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switch (phy->speed) {
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case 10:
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reg = QCA8K_PORT_STATUS_SPEED_10;
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reg = QCA8K_REG_PORT0_PAD_CTRL;
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break;
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case 100:
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reg = QCA8K_PORT_STATUS_SPEED_100;
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break;
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case 1000:
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reg = QCA8K_PORT_STATUS_SPEED_1000;
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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/* Internal PHY, nothing to do */
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return;
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case 6: /* 2nd CPU port / external PHY */
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if (state->interface != PHY_INTERFACE_MODE_RGMII &&
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state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
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state->interface != PHY_INTERFACE_MODE_SGMII &&
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state->interface != PHY_INTERFACE_MODE_1000BASEX)
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return;
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reg = QCA8K_REG_PORT6_PAD_CTRL;
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break;
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default:
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dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
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port, phy->speed);
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dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
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return;
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}
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/* Set duplex mode */
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if (phy->duplex == DUPLEX_FULL)
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reg |= QCA8K_PORT_STATUS_DUPLEX;
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if (port != 6 && phylink_autoneg_inband(mode)) {
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dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
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__func__);
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return;
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}
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/* Force flow control */
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if (dsa_is_cpu_port(ds, port))
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reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
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switch (state->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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/* RGMII mode means no delay so don't enable the delay */
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qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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/* RGMII_ID needs internal delay. This is enabled through
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* PORT5_PAD_CTRL for all ports, rather than individual port
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* registers
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*/
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qca8k_write(priv, reg,
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QCA8K_PORT_PAD_RGMII_EN |
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QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
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QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
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qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
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QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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/* Enable SGMII on the port */
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qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
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break;
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default:
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dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
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phy_modes(state->interface), port);
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return;
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}
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}
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static void
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qca8k_phylink_validate(struct dsa_switch *ds, int port,
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unsigned long *supported,
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struct phylink_link_state *state)
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{
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__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
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switch (port) {
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case 0: /* 1st CPU port */
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if (state->interface != PHY_INTERFACE_MODE_NA &&
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state->interface != PHY_INTERFACE_MODE_RGMII &&
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state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
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state->interface != PHY_INTERFACE_MODE_SGMII)
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goto unsupported;
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break;
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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/* Internal PHY */
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if (state->interface != PHY_INTERFACE_MODE_NA &&
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state->interface != PHY_INTERFACE_MODE_GMII)
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goto unsupported;
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break;
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case 6: /* 2nd CPU port / external PHY */
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if (state->interface != PHY_INTERFACE_MODE_NA &&
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state->interface != PHY_INTERFACE_MODE_RGMII &&
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state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
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state->interface != PHY_INTERFACE_MODE_SGMII &&
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state->interface != PHY_INTERFACE_MODE_1000BASEX)
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goto unsupported;
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break;
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default:
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unsupported:
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linkmode_zero(supported);
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return;
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}
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phylink_set_port_modes(mask);
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phylink_set(mask, Autoneg);
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phylink_set(mask, 1000baseT_Full);
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phylink_set(mask, 10baseT_Half);
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phylink_set(mask, 10baseT_Full);
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phylink_set(mask, 100baseT_Half);
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phylink_set(mask, 100baseT_Full);
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if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
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phylink_set(mask, 1000baseX_Full);
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phylink_set(mask, Pause);
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phylink_set(mask, Asym_Pause);
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linkmode_and(supported, supported, mask);
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linkmode_and(state->advertising, state->advertising, mask);
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}
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static int
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qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
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struct phylink_link_state *state)
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{
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struct qca8k_priv *priv = ds->priv;
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u32 reg;
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reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port));
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state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
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state->an_complete = state->link;
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state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
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state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
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DUPLEX_HALF;
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switch (reg & QCA8K_PORT_STATUS_SPEED) {
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case QCA8K_PORT_STATUS_SPEED_10:
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state->speed = SPEED_10;
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break;
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case QCA8K_PORT_STATUS_SPEED_100:
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state->speed = SPEED_100;
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break;
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case QCA8K_PORT_STATUS_SPEED_1000:
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state->speed = SPEED_1000;
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break;
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default:
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state->speed = SPEED_UNKNOWN;
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break;
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}
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state->pause = MLO_PAUSE_NONE;
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if (reg & QCA8K_PORT_STATUS_RXFLOW)
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state->pause |= MLO_PAUSE_RX;
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if (reg & QCA8K_PORT_STATUS_TXFLOW)
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state->pause |= MLO_PAUSE_TX;
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return 1;
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}
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static void
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qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
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phy_interface_t interface)
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{
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struct qca8k_priv *priv = ds->priv;
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/* Force link down before changing MAC options */
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qca8k_port_set_status(priv, port, 0);
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}
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static void
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qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
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phy_interface_t interface, struct phy_device *phydev,
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int speed, int duplex, bool tx_pause, bool rx_pause)
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{
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struct qca8k_priv *priv = ds->priv;
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u32 reg;
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if (phylink_autoneg_inband(mode)) {
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reg = QCA8K_PORT_STATUS_LINK_AUTO;
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} else {
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switch (speed) {
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case SPEED_10:
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reg = QCA8K_PORT_STATUS_SPEED_10;
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break;
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case SPEED_100:
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reg = QCA8K_PORT_STATUS_SPEED_100;
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break;
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case SPEED_1000:
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reg = QCA8K_PORT_STATUS_SPEED_1000;
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break;
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default:
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reg = QCA8K_PORT_STATUS_LINK_AUTO;
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break;
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}
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if (duplex == DUPLEX_FULL)
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reg |= QCA8K_PORT_STATUS_DUPLEX;
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if (rx_pause || dsa_is_cpu_port(ds, port))
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reg |= QCA8K_PORT_STATUS_RXFLOW;
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if (tx_pause || dsa_is_cpu_port(ds, port))
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reg |= QCA8K_PORT_STATUS_TXFLOW;
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}
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reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
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qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
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qca8k_port_set_status(priv, port, 1);
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}
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static void
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@ -937,13 +1049,11 @@ qca8k_port_enable(struct dsa_switch *ds, int port,
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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if (!dsa_is_user_port(ds, port))
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return 0;
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qca8k_port_set_status(priv, port, 1);
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priv->port_sts[port].enabled = 1;
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phy_support_asym_pause(phy);
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if (dsa_is_user_port(ds, port))
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phy_support_asym_pause(phy);
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return 0;
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}
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@ -1026,7 +1136,6 @@ qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
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static const struct dsa_switch_ops qca8k_switch_ops = {
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.get_tag_protocol = qca8k_get_tag_protocol,
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.setup = qca8k_setup,
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.adjust_link = qca8k_adjust_link,
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.get_strings = qca8k_get_strings,
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.get_ethtool_stats = qca8k_get_ethtool_stats,
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.get_sset_count = qca8k_get_sset_count,
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@ -1040,6 +1149,11 @@ static const struct dsa_switch_ops qca8k_switch_ops = {
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.port_fdb_add = qca8k_port_fdb_add,
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.port_fdb_del = qca8k_port_fdb_del,
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.port_fdb_dump = qca8k_port_fdb_dump,
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.phylink_validate = qca8k_phylink_validate,
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.phylink_mac_link_state = qca8k_phylink_mac_link_state,
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.phylink_mac_config = qca8k_phylink_mac_config,
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.phylink_mac_link_down = qca8k_phylink_mac_link_down,
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.phylink_mac_link_up = qca8k_phylink_mac_link_up,
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};
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static int
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