clk: samsung: exynosautov9: add cmu_peric1 clock support
Like CMU_PERIC0, this provides clocks for USI06 ~ USI11 and USI_I2C. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-10-chanho61.park@samsung.com
This commit is contained in:
Chanho Park
Sylwester Nawrocki
parent
f2dd366992
commit
b35f27fe73
@ -1385,6 +1385,257 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
|
||||
.clk_name = "dout_clkcmu_peric0_bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_PERIC1 --------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_PERIC1 (0x10800000) */
|
||||
#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
|
||||
#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x0610
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI 0x1000
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI 0x1004
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI 0x1008
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x100c
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1010
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x1014
|
||||
#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1018
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1800
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1804
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x1808
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x180c
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1810
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1814
|
||||
#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1818
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 0x2014
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2018
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 0x2038
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x203c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 0x2040
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x201c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2058
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x205c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2060
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x206c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2064
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2068
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2070
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2074
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
|
||||
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
|
||||
|
||||
static const unsigned long peric1_clk_regs[] __initconst = {
|
||||
PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
|
||||
PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
|
||||
CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
|
||||
CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_PERIC1 */
|
||||
PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_clkcmu_peric1_bus" };
|
||||
PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
|
||||
PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
|
||||
|
||||
static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
|
||||
MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
|
||||
mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
|
||||
MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
|
||||
mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
|
||||
/* USI06 ~ USI11 */
|
||||
MUX(CLK_MOUT_PERIC1_USI06_USI, "mout_peric1_usi06_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI07_USI, "mout_peric1_usi07_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI08_USI, "mout_peric1_usi08_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
|
||||
MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
|
||||
/* USI_I2C */
|
||||
MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
|
||||
mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock peric1_div_clks[] __initconst = {
|
||||
/* USI06 ~ USI11 */
|
||||
DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
|
||||
"mout_peric1_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
|
||||
"mout_peric1_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
|
||||
"mout_peric1_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
|
||||
"mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
|
||||
"mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
|
||||
0, 4),
|
||||
DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
|
||||
"mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
|
||||
0, 4),
|
||||
/* USI_I2C */
|
||||
DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
|
||||
"mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
|
||||
/* IPCLK */
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_0, "gout_peric1_ipclk_0",
|
||||
"dout_peric1_usi06_usi",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_1, "gout_peric1_ipclk_1",
|
||||
"dout_peric1_usi_i2c",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_2, "gout_peric1_ipclk_2",
|
||||
"dout_peric1_usi07_usi",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_3, "gout_peric1_ipclk_3",
|
||||
"dout_peric1_usi_i2c",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_4, "gout_peric1_ipclk_4",
|
||||
"dout_peric1_usi08_usi",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_5, "gout_peric1_ipclk_5",
|
||||
"dout_peric1_usi_i2c",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_6, "gout_peric1_ipclk_6",
|
||||
"dout_peric1_usi09_usi",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_7, "gout_peric1_ipclk_7",
|
||||
"dout_peric1_usi_i2c",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_8, "gout_peric1_ipclk_8",
|
||||
"dout_peric1_usi10_usi",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_9, "gout_peric1_ipclk_9",
|
||||
"dout_peric1_usi_i2c",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_10, "gout_peric1_ipclk_10",
|
||||
"dout_peric1_usi11_usi",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_IPCLK_11, "gout_peric1_ipclk_11",
|
||||
"dout_peric1_usi_i2c",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
|
||||
21, 0, 0),
|
||||
|
||||
/* PCLK */
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_0, "gout_peric1_pclk_0",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_3, "gout_peric1_pclk_3",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_4, "gout_peric1_pclk_4",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_5, "gout_peric1_pclk_5",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_6, "gout_peric1_pclk_6",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_7, "gout_peric1_pclk_7",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_8, "gout_peric1_pclk_8",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_9, "gout_peric1_pclk_9",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_10, "gout_peric1_pclk_10",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
|
||||
21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC1_PCLK_11, "gout_peric1_pclk_11",
|
||||
"mout_peric1_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
|
||||
21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
|
||||
.mux_clks = peric1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
|
||||
.div_clks = peric1_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(peric1_div_clks),
|
||||
.gate_clks = peric1_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
|
||||
.nr_clk_ids = PERIC1_NR_CLK,
|
||||
.clk_regs = peric1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
|
||||
.clk_name = "dout_clkcmu_peric1_bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_PERIS ---------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_PERIS (0x10020000) */
|
||||
@ -1456,6 +1707,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-peric0",
|
||||
.data = &peric0_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-peric1",
|
||||
.data = &peric1_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-peris",
|
||||
.data = &peris_cmu_info,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user