ARM: i.MX6: add i.MX6 specific L2 cache configuration
To improve the performance and power consumption add an i.MX6 specific L2 cache initialization. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] with two additional improvements: a) The L2X0_POWER_CTRL has only the two bits we set. So no need to read the register before. Remove the register read done in Freescale's patch. b) In the L2X0_PREFETCH_CTRL register, besides the double linefill (bit[30]), additionally enable the instruction and data prefetch (bit[29-28]). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
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@ -253,10 +253,44 @@ static void __init imx6q_map_io(void)
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imx_scu_map_io();
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imx_scu_map_io();
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}
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}
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#ifdef CONFIG_CACHE_L2X0
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static void __init imx6q_init_l2cache(void)
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{
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void __iomem *l2x0_base;
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struct device_node *np;
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unsigned int val;
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np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
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if (!np)
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goto out;
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l2x0_base = of_iomap(np, 0);
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if (!l2x0_base) {
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of_node_put(np);
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goto out;
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}
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/* Configure the L2 PREFETCH and POWER registers */
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val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
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val |= 0x70800000;
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writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
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val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
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writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
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iounmap(l2x0_base);
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of_node_put(np);
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out:
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l2x0_of_init(0, ~0UL);
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}
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#else
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static inline void imx6q_init_l2cache(void) {}
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#endif
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static void __init imx6q_init_irq(void)
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static void __init imx6q_init_irq(void)
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{
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{
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imx6q_init_revision();
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imx6q_init_revision();
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l2x0_of_init(0, ~0UL);
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imx6q_init_l2cache();
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imx_src_init();
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imx_src_init();
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imx_gpc_init();
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imx_gpc_init();
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irqchip_init();
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irqchip_init();
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