drm/amdgpu: add gpu harvest support for yellow carp (v2)
Register callback in gfxhub functions to program the bypass groups in gc_utcl2 corresponding to harvested SA. v2: update comments (Alex) Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -34,6 +34,7 @@ struct amdgpu_gfxhub_funcs {
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void (*set_fault_enable_default)(struct amdgpu_device *adev, bool value);
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void (*init)(struct amdgpu_device *adev);
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int (*get_xgmi_info)(struct amdgpu_device *adev);
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void (*utcl2_harvest)(struct amdgpu_device *adev);
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};
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struct amdgpu_gfxhub {
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@ -31,6 +31,9 @@
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#include "soc15_common.h"
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#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP 0x16f8
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#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX 0
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static const char *gfxhub_client_ids[] = {
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"CB/DB",
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"Reserved",
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@ -531,6 +534,42 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
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return 0;
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}
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static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
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{
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int i;
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u32 tmp = 0, disabled_sa = 0;
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u32 efuse_setting, vbios_setting;
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u32 max_sa_mask = amdgpu_gfx_create_bitmask(
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adev->gfx.config.max_sh_per_se *
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adev->gfx.config.max_shader_engines);
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if (adev->asic_type == CHIP_YELLOW_CARP) {
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/* Get SA disabled bitmap from eFuse setting */
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efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
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efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
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efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
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/* Get SA disabled bitmap from VBIOS setting */
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vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
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vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
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vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
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disabled_sa |= efuse_setting | vbios_setting;
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/* Make sure not to report harvested SAs beyond the max SA count */
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disabled_sa &= max_sa_mask;
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for (i = 0; disabled_sa > 0; i++) {
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if (disabled_sa & 1)
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tmp |= 0x3 << (i * 2);
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disabled_sa >>= 1;
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}
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disabled_sa = tmp;
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WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);
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}
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}
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const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
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.get_fb_location = gfxhub_v2_1_get_fb_location,
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.get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
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@ -540,4 +579,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
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.set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default,
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.init = gfxhub_v2_1_init,
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.get_xgmi_info = gfxhub_v2_1_get_xgmi_info,
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.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
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};
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@ -1059,6 +1059,13 @@ static int gmc_v10_0_hw_init(void *handle)
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/* The sequence of these two function calls matters.*/
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gmc_v10_0_init_golden_registers(adev);
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/*
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* harvestable groups in gc_utcl2 need to be programmed before any GFX block
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* register setup within GMC, or else system hang when harvesting SA.
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*/
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if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
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adev->gfxhub.funcs->utcl2_harvest(adev);
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r = gmc_v10_0_gart_enable(adev);
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if (r)
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return r;
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