usb: dwc2: Add Interpacket Gap(IPG) feature support
Added GHWCFG4_IPG_ISOC_SUPPORTED and DCFG_IPG_ISOC_SUPPORDED bits definitions to enable/disable IPG feature. Added ipg_isoc_en core parameter which will indicate IPG support enable/disable and initialize it. Signed-off-by: Grigor Tovmasyan <tovmasya@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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@ -380,6 +380,9 @@ enum dwc2_ep0_state {
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* is FS.
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* 0 - No (default)
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* 1 - Yes
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* @ipg_isoc_en Indicates the IPG supports is enabled or disabled.
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* 0 - Disable (default)
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* 1 - Enable
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* @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
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* 0 - No (default)
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* 1 - Yes
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@ -511,6 +514,7 @@ struct dwc2_core_params {
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bool hird_threshold_en;
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u8 hird_threshold;
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bool activate_stm_fs_transceiver;
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bool ipg_isoc_en;
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u16 max_packet_count;
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u32 max_transfer_size;
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u32 ahbcfg;
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@ -560,6 +564,12 @@ struct dwc2_core_params {
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* 0 - Slave only
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* 1 - External DMA
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* 2 - Internal DMA
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* @ipg_isoc_en This feature indicates that the controller supports
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* the worst-case scenario of Rx followed by Rx
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* Interpacket Gap (IPG) (32 bitTimes) as per the utmi
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* specification for any token following ISOC OUT token.
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* 0 - Don't support
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* 1 - Support
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* @power_optimized Are power optimizations enabled?
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* @num_dev_ep Number of device endpoints available
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* @num_dev_in_eps Number of device IN endpoints available
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@ -622,6 +632,7 @@ struct dwc2_hw_params {
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unsigned hibernation:1;
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unsigned utmi_phy_data_width:2;
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unsigned lpm_mode:1;
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unsigned ipg_isoc_en:1;
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u32 snpsid;
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u32 dev_ep_dirs;
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u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
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@ -710,6 +710,7 @@ static int params_show(struct seq_file *seq, void *v)
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print_param(seq, p, phy_ulpi_ddr);
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print_param(seq, p, phy_ulpi_ext_vbus);
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print_param(seq, p, i2c_enable);
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print_param(seq, p, ipg_isoc_en);
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print_param(seq, p, ulpi_fs_ls);
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print_param(seq, p, host_support_fs_ls_low_power);
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print_param(seq, p, host_ls_low_power_phy_clk);
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@ -3236,6 +3236,9 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
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dcfg |= DCFG_DEVSPD_HS;
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}
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if (hsotg->params.ipg_isoc_en)
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dcfg |= DCFG_IPG_ISOC_SUPPORDED;
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dwc2_writel(dcfg, hsotg->regs + DCFG);
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/* Clear any pending OTG interrupts */
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@ -311,6 +311,7 @@
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#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
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#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
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#define GHWCFG4_ACG_SUPPORTED BIT(12)
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#define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11)
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#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
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#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
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#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
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@ -424,6 +425,7 @@
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#define DCFG_EPMISCNT_SHIFT 18
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#define DCFG_EPMISCNT_LIMIT 0x1f
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#define DCFG_EPMISCNT(_x) ((_x) << 18)
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#define DCFG_IPG_ISOC_SUPPORDED BIT(17)
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#define DCFG_PERFRINT_MASK (0x3 << 11)
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#define DCFG_PERFRINT_SHIFT 11
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#define DCFG_PERFRINT_LIMIT 0x3
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@ -298,6 +298,7 @@ static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
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p->besl = true;
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p->hird_threshold_en = true;
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p->hird_threshold = 4;
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p->ipg_isoc_en = false;
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p->max_packet_count = hw->max_packet_count;
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p->max_transfer_size = hw->max_transfer_size;
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
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@ -579,6 +580,7 @@ static void dwc2_check_params(struct dwc2_hsotg *hsotg)
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CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
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CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
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CHECK_BOOL(i2c_enable, hw->i2c_enable);
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CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
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CHECK_BOOL(acg_enable, hw->acg_enable);
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CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
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CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
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@ -772,6 +774,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
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hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
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GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
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hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
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hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
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/* fifo sizes */
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hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
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