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irqchip fixes for 5.13, take #1

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- Fix PXA Mainstone CPLD irq allocation in legacy mode
 - Restrict the Apple AIC controller to the Apple platform
 - Remove a few supperfluous messages on devm_ioremap_resource() failure
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Merge tag 'irqchip-fixes-5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip fixes from Marc Zyngier:

 - Fix PXA Mainstone CPLD irq allocation in legacy mode
 - Restrict the Apple AIC controller to the Apple platform
 - Remove a few supperfluous messages on devm_ioremap_resource() failure

Link: https://lore.kernel.org/r/20210516122217.13234-1-maz@kernel.org
This commit is contained in:
Thomas Gleixner 2021-05-17 19:57:47 +02:00
commit b4764905ea
5 changed files with 10 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/mach-pxa/pxa_cplds_irqs.c
View File

@ -121,8 +121,13 @@ static int cplds_probe(struct platform_device *pdev)
return fpga->irq; return fpga->irq;
base_irq = platform_get_irq(pdev, 1); base_irq = platform_get_irq(pdev, 1);
if (base_irq < 0) if (base_irq < 0) {
base_irq = 0; base_irq = 0;
} else {
ret = devm_irq_alloc_descs(&pdev->dev, base_irq, base_irq, CPLDS_NB_IRQ, 0);
if (ret < 0)
return ret;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fpga->base = devm_ioremap_resource(&pdev->dev, res); fpga->base = devm_ioremap_resource(&pdev->dev, res);

2
drivers/irqchip/Kconfig
View File

@ -596,7 +596,7 @@ config IRQ_IDT3243X
config APPLE_AIC config APPLE_AIC
bool "Apple Interrupt Controller (AIC)" bool "Apple Interrupt Controller (AIC)"
depends on ARM64 depends on ARM64
default ARCH_APPLE depends on ARCH_APPLE || COMPILE_TEST
help help
Support for the Apple Interrupt Controller found on Apple Silicon SoCs, Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
such as the M1. such as the M1.

4
drivers/irqchip/irq-mvebu-icu.c
View File

@ -359,10 +359,8 @@ static int mvebu_icu_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
icu->base = devm_ioremap_resource(&pdev->dev, res); icu->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(icu->base)) { if (IS_ERR(icu->base))
dev_err(&pdev->dev, "Failed to map icu base address.\n");
return PTR_ERR(icu->base); return PTR_ERR(icu->base);
}
/* /*
* Legacy bindings: ICU is one node with one MSI parent: force manually * Legacy bindings: ICU is one node with one MSI parent: force manually

4
drivers/irqchip/irq-mvebu-sei.c
View File

@ -384,10 +384,8 @@ static int mvebu_sei_probe(struct platform_device *pdev)
sei->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); sei->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
sei->base = devm_ioremap_resource(sei->dev, sei->res); sei->base = devm_ioremap_resource(sei->dev, sei->res);
if (IS_ERR(sei->base)) { if (IS_ERR(sei->base))
dev_err(sei->dev, "Failed to remap SEI resource\n");
return PTR_ERR(sei->base); return PTR_ERR(sei->base);
}
/* Retrieve the SEI capabilities with the interrupt ranges */ /* Retrieve the SEI capabilities with the interrupt ranges */
sei->caps = of_device_get_match_data(&pdev->dev); sei->caps = of_device_get_match_data(&pdev->dev);

4
drivers/irqchip/irq-stm32-exti.c
View File

@ -892,10 +892,8 @@ static int stm32_exti_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
host_data->base = devm_ioremap_resource(dev, res); host_data->base = devm_ioremap_resource(dev, res);
if (IS_ERR(host_data->base)) { if (IS_ERR(host_data->base))
dev_err(dev, "Unable to map registers\n");
return PTR_ERR(host_data->base); return PTR_ERR(host_data->base);
}
for (i = 0; i < drv_data->bank_nr; i++) for (i = 0; i < drv_data->bank_nr; i++)
stm32_exti_chip_init(host_data, i, np); stm32_exti_chip_init(host_data, i, np);