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qlcnic: update oncard memory size check

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All QLogic converged NICs have 128-bit 128MB on card memory.
Fix the limit check from 64MB to 128MB and remove unnecessary
64-bit read/write checks.

Signed-off-by: Dhananjay Phadke <dhananjay.phadke@qlogic.com>
Signed-off-by: Amit Kumar Salecha <amit.salecha@qlogic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dhananjay Phadke 2010-04-01 19:01:30 +00:00 committed by David S. Miller
parent 897e8c7c45
commit b47acacd7c
2 changed files with 26 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/qlcnic/qlcnic_hdr.h
View File

@ -449,7 +449,7 @@ enum {
#define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL) #define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL)
#define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL) #define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL)
#define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL) #define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL)
#define QLCNIC_ADDR_QDR_NET_MAX_P3 (0x0000000303ffffffULL) #define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
/* /*
* Register offsets for MN * Register offsets for MN

57
drivers/net/qlcnic/qlcnic_hw.c
View File

@ -963,7 +963,6 @@ qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
{ {
int i, j, ret; int i, j, ret;
u32 temp, off8; u32 temp, off8;
u64 stride;
void __iomem *mem_crb; void __iomem *mem_crb;
/* Only 64-bit aligned access */ /* Only 64-bit aligned access */
@ -972,7 +971,7 @@ qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
/* P3 onward, test agent base for MIU and SIU is same */ /* P3 onward, test agent base for MIU and SIU is same */
if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET, if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
QLCNIC_ADDR_QDR_NET_MAX_P3)) { QLCNIC_ADDR_QDR_NET_MAX)) {
mem_crb = qlcnic_get_ioaddr(adapter, mem_crb = qlcnic_get_ioaddr(adapter,
QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE); QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
goto correct; goto correct;
@ -990,9 +989,7 @@ qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
return -EIO; return -EIO;
correct: correct:
stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8; off8 = off & ~0xf;
off8 = off & ~(stride-1);
mutex_lock(&adapter->ahw.mem_lock); mutex_lock(&adapter->ahw.mem_lock);
@ -1000,30 +997,28 @@ correct:
writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
i = 0; i = 0;
if (stride == 16) { writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); writel((TA_CTL_START | TA_CTL_ENABLE),
writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
(mem_crb + TEST_AGT_CTRL));
for (j = 0; j < MAX_CTL_CHECK; j++) { for (j = 0; j < MAX_CTL_CHECK; j++) {
temp = readl(mem_crb + TEST_AGT_CTRL); temp = readl(mem_crb + TEST_AGT_CTRL);
if ((temp & TA_CTL_BUSY) == 0) if ((temp & TA_CTL_BUSY) == 0)
break; break;
}
if (j >= MAX_CTL_CHECK) {
ret = -EIO;
goto done;
}
i = (off & 0xf) ? 0 : 2;
writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
mem_crb + MIU_TEST_AGT_WRDATA(i));
writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
mem_crb + MIU_TEST_AGT_WRDATA(i+1));
i = (off & 0xf) ? 2 : 0;
} }
if (j >= MAX_CTL_CHECK) {
ret = -EIO;
goto done;
}
i = (off & 0xf) ? 0 : 2;
writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
mem_crb + MIU_TEST_AGT_WRDATA(i));
writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
mem_crb + MIU_TEST_AGT_WRDATA(i+1));
i = (off & 0xf) ? 2 : 0;
writel(data & 0xffffffff, writel(data & 0xffffffff,
mem_crb + MIU_TEST_AGT_WRDATA(i)); mem_crb + MIU_TEST_AGT_WRDATA(i));
writel((data >> 32) & 0xffffffff, writel((data >> 32) & 0xffffffff,
@ -1059,7 +1054,7 @@ qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
{ {
int j, ret; int j, ret;
u32 temp, off8; u32 temp, off8;
u64 val, stride; u64 val;
void __iomem *mem_crb; void __iomem *mem_crb;
/* Only 64-bit aligned access */ /* Only 64-bit aligned access */
@ -1068,7 +1063,7 @@ qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
/* P3 onward, test agent base for MIU and SIU is same */ /* P3 onward, test agent base for MIU and SIU is same */
if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET, if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
QLCNIC_ADDR_QDR_NET_MAX_P3)) { QLCNIC_ADDR_QDR_NET_MAX)) {
mem_crb = qlcnic_get_ioaddr(adapter, mem_crb = qlcnic_get_ioaddr(adapter,
QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE); QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
goto correct; goto correct;
@ -1088,9 +1083,7 @@ qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
return -EIO; return -EIO;
correct: correct:
stride = QLCNIC_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8; off8 = off & ~0xf;
off8 = off & ~(stride-1);
mutex_lock(&adapter->ahw.mem_lock); mutex_lock(&adapter->ahw.mem_lock);
@ -1112,7 +1105,7 @@ correct:
ret = -EIO; ret = -EIO;
} else { } else {
off8 = MIU_TEST_AGT_RDDATA_LO; off8 = MIU_TEST_AGT_RDDATA_LO;
if ((stride == 16) && (off & 0xf)) if (off & 0xf)
off8 = MIU_TEST_AGT_RDDATA_UPPER_LO; off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
temp = readl(mem_crb + off8 + 4); temp = readl(mem_crb + off8 + 4);