ARM: dts: rockchip: Enable gmac for XPI-3128
Add the required properties and enable the gmac node for XPI-3128 board. The minimum reset timing requirements for the phy have been taken from DP83848J's datasheet [0] [0] https://www.ti.com/lit/ds/symlink/dp83848j.pdf Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20231202124158.65615-4-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -11,6 +11,7 @@
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compatible = "geniatech,xpi-3128", "rockchip,rk3128";
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aliases {
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ethernet0 = &gmac;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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@ -255,6 +256,18 @@
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status = "okay";
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};
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&gmac {
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clock_in_out = "output";
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phy-supply = <&vcc_lan>;
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phy-mode = "rmii";
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phy-handle = <&phy0>;
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assigned-clocks = <&cru SCLK_MAC_SRC>;
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assigned-clock-rates= <50000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&rmii_pins>;
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status = "okay";
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};
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&gpio0 {
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gpio-line-names = /* GPIO0 A0-A7 */
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"", "", "HEADER_5", "HEADER_3",
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@ -315,6 +328,21 @@
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"", "", "", "";
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};
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&mdio {
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phy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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max-speed = <100>;
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/* T2.2.4 min. 1 us */
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reset-assert-us = <10>;
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/* T2.2.1 + T2.2.2 + T2.2.3 min. 6.05 us */
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reset-deassert-us = <20>;
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reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&dp83848c_rst>;
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};
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};
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&pinctrl {
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dp83848c {
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dp83848c_rst: dp83848c-rst {
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