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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

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The phylink conflict was between a bug fix by Russell King
to make sure we have a consistent PHY interface mode, and
a change in net-next to pull some code in phylink_resolve()
into the helper functions phylink_mac_link_{up,down}()

On the dp83867 side it's mostly overlapping changes, with
the 'net' side removing a condition that was supposed to
trigger for RGMII but because of how it was coded never
actually could trigger.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-05-31 10:49:43 -07:00
commit b4b12b0d2f
1459 changed files with 5338 additions and 15909 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
Documentation/ABI/testing/sysfs-bus-mdio
View File

@ -1,29 +0,0 @@
What: /sys/bus/mdio_bus/devices/.../phy_id
Date: November 2012
KernelVersion: 3.8
Contact: netdev@vger.kernel.org
Description:
This attribute contains the 32-bit PHY Identifier as reported
by the device during bus enumeration, encoded in hexadecimal.
This ID is used to match the device with the appropriate
driver.
What: /sys/bus/mdio_bus/devices/.../phy_interface
Date: February 2014
KernelVersion: 3.15
Contact: netdev@vger.kernel.org
Description:
This attribute contains the PHY interface as configured by the
Ethernet driver during bus enumeration, encoded in string.
This interface mode is used to configure the Ethernet MAC with the
appropriate mode for its data lines to the PHY hardware.
What: /sys/bus/mdio_bus/devices/.../phy_has_fixups
Date: February 2014
KernelVersion: 3.15
Contact: netdev@vger.kernel.org
Description:
This attribute contains the boolean value whether a given PHY
device has had any "fixup" workaround running on it, encoded as
a boolean. This information is provided to help troubleshooting
PHY configurations.

19
Documentation/ABI/testing/sysfs-class-net-phydev
View File

@ -11,24 +11,31 @@ Date: February 2014
KernelVersion: 3.15 KernelVersion: 3.15
Contact: netdev@vger.kernel.org Contact: netdev@vger.kernel.org
Description: Description:
Boolean value indicating whether the PHY device has This attribute contains the boolean value whether a given PHY
any fixups registered against it (phy_register_fixup) device has had any "fixup" workaround running on it, encoded as
a boolean. This information is provided to help troubleshooting
PHY configurations.
What: /sys/class/mdio_bus/<bus>/<device>/phy_id What: /sys/class/mdio_bus/<bus>/<device>/phy_id
Date: November 2012 Date: November 2012
KernelVersion: 3.8 KernelVersion: 3.8
Contact: netdev@vger.kernel.org Contact: netdev@vger.kernel.org
Description: Description:
32-bit hexadecimal value corresponding to the PHY device's OUI, This attribute contains the 32-bit PHY Identifier as reported
model and revision number. by the device during bus enumeration, encoded in hexadecimal.
This ID is used to match the device with the appropriate
driver.
What: /sys/class/mdio_bus/<bus>/<device>/phy_interface What: /sys/class/mdio_bus/<bus>/<device>/phy_interface
Date: February 2014 Date: February 2014
KernelVersion: 3.15 KernelVersion: 3.15
Contact: netdev@vger.kernel.org Contact: netdev@vger.kernel.org
Description: Description:
String value indicating the PHY interface, possible This attribute contains the PHY interface as configured by the
values are:. Ethernet driver during bus enumeration, encoded in string.
This interface mode is used to configure the Ethernet MAC with the
appropriate mode for its data lines to the PHY hardware.
Possible values are:
<empty> (not available), mii, gmii, sgmii, tbi, rev-mii, <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui, xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,

1
Documentation/admin-guide/mm/index.rst
View File

@ -31,6 +31,7 @@ the Linux memory management.
ksm ksm
memory-hotplug memory-hotplug
numa_memory_policy numa_memory_policy
numaperf
pagemap pagemap
soft-dirty soft-dirty
transhuge transhuge

2
Documentation/admin-guide/mm/numaperf.rst
View File

@ -15,7 +15,7 @@ characteristics. Some memory may share the same node as a CPU, and others
are provided as memory only nodes. While memory only nodes do not provide are provided as memory only nodes. While memory only nodes do not provide
CPUs, they may still be local to one or more compute nodes relative to CPUs, they may still be local to one or more compute nodes relative to
other nodes. The following diagram shows one such example of two compute other nodes. The following diagram shows one such example of two compute
nodes with local memory and a memory only node for each of compute node: nodes with local memory and a memory only node for each of compute node::
+------------------+ +------------------+ +------------------+ +------------------+
| Compute Node 0 +-----+ Compute Node 1 | | Compute Node 0 +-----+ Compute Node 1 |

9
Documentation/arm64/silicon-errata.txt
View File

@ -58,13 +58,14 @@ stable kernels.
| ARM | Cortex-A72 | #853709 | N/A | | ARM | Cortex-A72 | #853709 | N/A |
| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
| ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 | | ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
| ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 | | ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 |
| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 | | ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
| ARM | Neoverse-N1 | #1188873 | ARM64_ERRATUM_1188873 | | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
| ARM | MMU-500 | #841119,#826419 | N/A | | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
| ARM | MMU-500 | #841119,826419 | N/A |
| | | | | | | | | |
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | | Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |

2
Documentation/conf.py
View File

@ -37,7 +37,7 @@ needs_sphinx = '1.3'
extensions = ['kerneldoc', 'rstFlatTable', 'kernel_include', 'cdomain', 'kfigure', 'sphinx.ext.ifconfig'] extensions = ['kerneldoc', 'rstFlatTable', 'kernel_include', 'cdomain', 'kfigure', 'sphinx.ext.ifconfig']
# The name of the math extension changed on Sphinx 1.4 # The name of the math extension changed on Sphinx 1.4
if major == 1 and minor > 3: if (major == 1 and minor > 3) or (major > 1):
extensions.append("sphinx.ext.imgmath") extensions.append("sphinx.ext.imgmath")
else: else:
extensions.append("sphinx.ext.pngmath") extensions.append("sphinx.ext.pngmath")

2
Documentation/devicetree/bindings/Makefile
View File

@ -5,7 +5,7 @@ DT_MK_SCHEMA ?= dt-mk-schema
DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u) DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u)
quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<) quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \ cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
$(DT_EXTRACT_EX) $< > $@ $(DT_EXTRACT_EX) $< > $@
$(obj)/%.example.dts: $(src)/%.yaml FORCE $(obj)/%.example.dts: $(src)/%.yaml FORCE

4
Documentation/devicetree/bindings/arm/arm-boards
View File

@ -216,7 +216,7 @@ Example:
#size-cells = <0>; #size-cells = <0>;
A57_0: cpu@0 { A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x0 0x0>; reg = <0x0 0x0>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
@ -225,7 +225,7 @@ Example:
..... .....
A53_0: cpu@100 { A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x0 0x100>; reg = <0x0 0x100>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";

12
Documentation/devicetree/bindings/arm/cpu-capacity.txt
View File

@ -118,7 +118,7 @@ cpus {
}; };
A57_0: cpu@0 { A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x0 0x0>; reg = <0x0 0x0>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
@ -129,7 +129,7 @@ cpus {
}; };
A57_1: cpu@1 { A57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8"; compatible = "arm,cortex-a57";
reg = <0x0 0x1>; reg = <0x0 0x1>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
@ -140,7 +140,7 @@ cpus {
}; };
A53_0: cpu@100 { A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x0 0x100>; reg = <0x0 0x100>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
@ -151,7 +151,7 @@ cpus {
}; };
A53_1: cpu@101 { A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x0 0x101>; reg = <0x0 0x101>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
@ -162,7 +162,7 @@ cpus {
}; };
A53_2: cpu@102 { A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x0 0x102>; reg = <0x0 0x102>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";
@ -173,7 +173,7 @@ cpus {
}; };
A53_3: cpu@103 { A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53";
reg = <0x0 0x103>; reg = <0x0 0x103>;
device_type = "cpu"; device_type = "cpu";
enable-method = "psci"; enable-method = "psci";

2
Documentation/devicetree/bindings/arm/omap/crossbar.txt
View File

@ -41,7 +41,7 @@ Examples:
Consumer: Consumer:
======== ========
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
further details. further details.
An interrupt consumer on an SoC using crossbar will use: An interrupt consumer on an SoC using crossbar will use:

2
Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
View File

@ -35,7 +35,7 @@ board device tree, including the system base clock, as selected by XOM[0]
pin of the SoC. Refer to generic fixed rate clock bindings pin of the SoC. Refer to generic fixed rate clock bindings
documentation[1] for more information how to specify these clocks. documentation[1] for more information how to specify these clocks.
[1] Documentation/devicetree/bindings/clock/fixed-clock.txt [1] Documentation/devicetree/bindings/clock/fixed-clock.yaml
Example: Clock controller node: Example: Clock controller node:

24
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
View File

@ -92,6 +92,8 @@ properties:
minItems: 2 minItems: 2
maxItems: 4 maxItems: 4
ranges: true
interrupts: interrupts:
description: Interrupt source of the parent interrupt controller on description: Interrupt source of the parent interrupt controller on
secondary GICs, or VGIC maintenance interrupt on primary GIC (see secondary GICs, or VGIC maintenance interrupt on primary GIC (see
@ -197,28 +199,28 @@ examples:
interrupt-controller@e1101000 { interrupt-controller@e1101000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <2>; #address-cells = <1>;
#size-cells = <2>; #size-cells = <1>;
interrupt-controller; interrupt-controller;
interrupts = <1 8 0xf04>; interrupts = <1 8 0xf04>;
ranges = <0 0 0 0xe1100000 0 0x100000>; ranges = <0 0xe1100000 0x100000>;
reg = <0x0 0xe1110000 0 0x01000>, reg = <0xe1110000 0x01000>,
<0x0 0xe112f000 0 0x02000>, <0xe112f000 0x02000>,
<0x0 0xe1140000 0 0x10000>, <0xe1140000 0x10000>,
<0x0 0xe1160000 0 0x10000>; <0xe1160000 0x10000>;
v2m0: v2m@8000 { v2m0: v2m@80000 {
compatible = "arm,gic-v2m-frame"; compatible = "arm,gic-v2m-frame";
msi-controller; msi-controller;
reg = <0x0 0x80000 0 0x1000>; reg = <0x80000 0x1000>;
}; };
//... //...
v2mN: v2m@9000 { v2mN: v2m@90000 {
compatible = "arm,gic-v2m-frame"; compatible = "arm,gic-v2m-frame";
msi-controller; msi-controller;
reg = <0x0 0x90000 0 0x1000>; reg = <0x90000 0x1000>;
}; };
}; };
... ...

2
Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt
View File

@ -23,7 +23,7 @@ Required properties:
- marvell,spi-base : List of GIC base SPI interrupts, one for each - marvell,spi-base : List of GIC base SPI interrupts, one for each
ODMI frame. Those SPI interrupts are 0-based, ODMI frame. Those SPI interrupts are 0-based,
i.e marvell,spi-base = <128> will use SPI #96. i.e marvell,spi-base = <128> will use SPI #96.
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
for details about the GIC Device Tree binding. for details about the GIC Device Tree binding.
Example: Example:

2
Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt
View File

@ -15,7 +15,7 @@ Optional properties:
- power-supply: specifies the power source. It can either be a regulator - power-supply: specifies the power source. It can either be a regulator
or a gpio which enables a regulator, i.e. a regulator-fixed as or a gpio which enables a regulator, i.e. a regulator-fixed as
described in described in
Documentation/devicetree/bindings/regulator/fixed-regulator.txt Documentation/devicetree/bindings/regulator/fixed-regulator.yaml
Example: Example:

2
Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
View File

@ -24,7 +24,7 @@ Optional children nodes:
Children nodes represent the available nand chips. Children nodes represent the available nand chips.
Other properties: Other properties:
see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
Example demonstrate on AXG SoC: Example demonstrate on AXG SoC:

6
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
View File

@ -101,12 +101,12 @@ Required properties:
number (e.g., 0, 1, 2, etc.) number (e.g., 0, 1, 2, etc.)
- #address-cells : see partition.txt - #address-cells : see partition.txt
- #size-cells : see partition.txt - #size-cells : see partition.txt
- nand-ecc-strength : see nand.txt - nand-ecc-strength : see nand-controller.yaml
- nand-ecc-step-size : must be 512 or 1024. See nand.txt - nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml
Optional properties: Optional properties:
- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this - nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
chip-select. See nand.txt chip-select. See nand-controller.yaml
- brcm,nand-oob-sector-size : integer, to denote the spare area sector size - brcm,nand-oob-sector-size : integer, to denote the spare area sector size
expected for the ECC layout in use. This size, in expected for the ECC layout in use. This size, in
addition to the strength and step-size, addition to the strength and step-size,

6
Documentation/devicetree/bindings/mtd/denali-nand.txt
View File

@ -22,16 +22,16 @@ Sub-nodes:
select is connected. select is connected.
Optional properties: Optional properties:
- nand-ecc-step-size: see nand.txt for details. - nand-ecc-step-size: see nand-controller.yaml for details.
If present, the value must be If present, the value must be
512 for "altr,socfpga-denali-nand" 512 for "altr,socfpga-denali-nand"
1024 for "socionext,uniphier-denali-nand-v5a" 1024 for "socionext,uniphier-denali-nand-v5a"
1024 for "socionext,uniphier-denali-nand-v5b" 1024 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-strength: see nand.txt for details. Valid values are: - nand-ecc-strength: see nand-controller.yaml for details. Valid values are:
8, 15 for "altr,socfpga-denali-nand" 8, 15 for "altr,socfpga-denali-nand"
8, 16, 24 for "socionext,uniphier-denali-nand-v5a" 8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
8, 16 for "socionext,uniphier-denali-nand-v5b" 8, 16 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-maximize: see nand.txt for details - nand-ecc-maximize: see nand-controller.yaml for details
The chip nodes may optionally contain sub-nodes describing partitions of the The chip nodes may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail. address space. See partition.txt for more detail.

6
Documentation/devicetree/bindings/mtd/fsmc-nand.txt
View File

@ -30,9 +30,9 @@ Optional properties:
command is asserted. Zero means one cycle, 255 means 256 command is asserted. Zero means one cycle, 255 means 256
cycles. cycles.
- bank: default NAND bank to use (0-3 are valid, 0 is the default). - bank: default NAND bank to use (0-3 are valid, 0 is the default).
- nand-ecc-mode : see nand.txt - nand-ecc-mode : see nand-controller.yaml
- nand-ecc-strength : see nand.txt - nand-ecc-strength : see nand-controller.yaml
- nand-ecc-step-size : see nand.txt - nand-ecc-step-size : see nand-controller.yaml
Can support 1-bit HW ECC (default) or if stronger correction is required, Can support 1-bit HW ECC (default) or if stronger correction is required,
software-based BCH. software-based BCH.

2
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
View File

@ -8,7 +8,7 @@ explained in a separate documents - please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
For NAND specific properties such as ECC modes or bus width, please refer to For NAND specific properties such as ECC modes or bus width, please refer to
Documentation/devicetree/bindings/mtd/nand.txt Documentation/devicetree/bindings/mtd/nand-controller.yaml
Required properties: Required properties:

2
Documentation/devicetree/bindings/mtd/hisi504-nand.txt
View File

@ -7,7 +7,7 @@ Required properties:
NAND controller's registers. The second contains base NAND controller's registers. The second contains base
physical address and size of NAND controller's buffer. physical address and size of NAND controller's buffer.
- interrupts: Interrupt number for nfc. - interrupts: Interrupt number for nfc.
- nand-bus-width: See nand.txt. - nand-bus-width: See nand-controller.yaml.
- nand-ecc-mode: Support none and hw ecc mode. - nand-ecc-mode: Support none and hw ecc mode.
- #address-cells: Partition address, should be set 1. - #address-cells: Partition address, should be set 1.
- #size-cells: Partition size, should be set 1. - #size-cells: Partition size, should be set 1.

14
Documentation/devicetree/bindings/mtd/marvell-nand.txt
View File

@ -36,29 +36,29 @@ Children nodes represent the available NAND chips.
Required properties: Required properties:
- reg: shall contain the native Chip Select ids (0-3). - reg: shall contain the native Chip Select ids (0-3).
- nand-rb: see nand.txt (0-1). - nand-rb: see nand-controller.yaml (0-1).
Optional properties: Optional properties:
- marvell,nand-keep-config: orders the driver not to take the timings - marvell,nand-keep-config: orders the driver not to take the timings
from the core and leaving them completely untouched. Bootloader from the core and leaving them completely untouched. Bootloader
timings will then be used. timings will then be used.
- label: MTD name. - label: MTD name.
- nand-on-flash-bbt: see nand.txt. - nand-on-flash-bbt: see nand-controller.yaml.
- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified. - nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
- nand-ecc-algo: see nand.txt. This property is essentially useful when - nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
not using hardware ECC. Howerver, it may be added when using hardware not using hardware ECC. Howerver, it may be added when using hardware
ECC for clarification but will be ignored by the driver because ECC ECC for clarification but will be ignored by the driver because ECC
mode is chosen depending on the page size and the strength required by mode is chosen depending on the page size and the strength required by
the NAND chip. This value may be overwritten with nand-ecc-strength the NAND chip. This value may be overwritten with nand-ecc-strength
property. property.
- nand-ecc-strength: see nand.txt. - nand-ecc-strength: see nand-controller.yaml.
- nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
step size will shrink or grow in order to fit the required strength. step size will shrink or grow in order to fit the required strength.
Step sizes are not completely random for all and follow certain Step sizes are not completely random for all and follow certain
patterns described in AN-379, "Marvell SoC NFC ECC". patterns described in AN-379, "Marvell SoC NFC ECC".
See Documentation/devicetree/bindings/mtd/nand.txt for more details on See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
generic bindings. generic bindings.

6
Documentation/devicetree/bindings/mtd/mxc-nand.txt
View File

@ -4,9 +4,9 @@ Required properties:
- compatible: "fsl,imxXX-nand" - compatible: "fsl,imxXX-nand"
- reg: address range of the nfc block - reg: address range of the nfc block
- interrupts: irq to be used - interrupts: irq to be used
- nand-bus-width: see nand.txt - nand-bus-width: see nand-controller.yaml
- nand-ecc-mode: see nand.txt - nand-ecc-mode: see nand-controller.yaml
- nand-on-flash-bbt: see nand.txt - nand-on-flash-bbt: see nand-controller.yaml
Example: Example:

6
Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
View File

@ -26,14 +26,14 @@ Optional children node properties:
"hw" is supported. "hw" is supported.
- nand-ecc-algo: string, algorithm of NAND ECC. - nand-ecc-algo: string, algorithm of NAND ECC.
Supported values with "hw" ECC mode are: "rs", "bch". Supported values with "hw" ECC mode are: "rs", "bch".
- nand-bus-width : See nand.txt - nand-bus-width : See nand-controller.yaml
- nand-on-flash-bbt: See nand.txt - nand-on-flash-bbt: See nand-controller.yaml
- nand-ecc-strength: integer representing the number of bits to correct - nand-ecc-strength: integer representing the number of bits to correct
per ECC step (always 512). Supported strength using HW ECC per ECC step (always 512). Supported strength using HW ECC
modes are: modes are:
- RS: 4, 6, 8 - RS: 4, 6, 8
- BCH: 4, 8, 14, 16 - BCH: 4, 8, 14, 16
- nand-ecc-maximize: See nand.txt - nand-ecc-maximize: See nand-controller.yaml
- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
are chosen. are chosen.
- wp-gpios: GPIO specifier for the write protect pin. - wp-gpios: GPIO specifier for the write protect pin.

2
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@ -1,6 +1,6 @@
* Oxford Semiconductor OXNAS NAND Controller * Oxford Semiconductor OXNAS NAND Controller
Please refer to nand.txt for generic information regarding MTD NAND bindings. Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
Required properties: Required properties:
- compatible: "oxsemi,ox820-nand" - compatible: "oxsemi,ox820-nand"

4
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@ -47,8 +47,8 @@ Required properties:
- #size-cells: see partition.txt - #size-cells: see partition.txt
Optional properties: Optional properties:
- nand-bus-width: see nand.txt - nand-bus-width: see nand-controller.yaml
- nand-ecc-strength: see nand.txt. If not specified, then ECC strength will - nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
be used according to chip requirement and available be used according to chip requirement and available
OOB size. OOB size.

6
Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt
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@ -6,7 +6,7 @@ Required properties:
"samsung,s3c2412-nand" "samsung,s3c2412-nand"
"samsung,s3c2440-nand" "samsung,s3c2440-nand"
- reg : register's location and length. - reg : register's location and length.
- #address-cells, #size-cells : see nand.txt - #address-cells, #size-cells : see nand-controller.yaml
- clocks : phandle to the nand controller clock - clocks : phandle to the nand controller clock
- clock-names : must contain "nand" - clock-names : must contain "nand"
@ -14,8 +14,8 @@ Optional child nodes:
Child nodes representing the available nand chips. Child nodes representing the available nand chips.
Optional child properties: Optional child properties:
- nand-ecc-mode : see nand.txt - nand-ecc-mode : see nand-controller.yaml
- nand-on-flash-bbt : see nand.txt - nand-on-flash-bbt : see nand-controller.yaml
Each child device node may optionally contain a 'partitions' sub-node, Each child device node may optionally contain a 'partitions' sub-node,
which further contains sub-nodes describing the flash partition mapping. which further contains sub-nodes describing the flash partition mapping.

6
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@ -24,9 +24,9 @@ Required properties:
- reg: describes the CS lines assigned to the NAND device. - reg: describes the CS lines assigned to the NAND device.
Optional properties: Optional properties:
- nand-on-flash-bbt: see nand.txt - nand-on-flash-bbt: see nand-controller.yaml
- nand-ecc-strength: see nand.txt - nand-ecc-strength: see nand-controller.yaml
- nand-ecc-step-size: see nand.txt - nand-ecc-step-size: see nand-controller.yaml
The following ECC strength and step size are currently supported: The following ECC strength and step size are currently supported:
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming) - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)

2
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@ -11,7 +11,7 @@ Required properties:
- #size-cells: <0> - #size-cells: <0>
Children nodes represent the available NAND chips. Children nodes represent the available NAND chips.
See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
Example: Example:

8
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@ -25,14 +25,14 @@ only handle one NAND chip.
Required properties: Required properties:
- compatible: Should be set to "fsl,vf610-nfc-cs". - compatible: Should be set to "fsl,vf610-nfc-cs".
- nand-bus-width: see nand.txt - nand-bus-width: see nand-controller.yaml
- nand-ecc-mode: see nand.txt - nand-ecc-mode: see nand-controller.yaml
Required properties for hardware ECC: Required properties for hardware ECC:
- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt) - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
- nand-ecc-step-size: step size equals page size, currently only 2k pages are - nand-ecc-step-size: step size equals page size, currently only 2k pages are
supported supported
- nand-on-flash-bbt: see nand.txt - nand-on-flash-bbt: see nand-controller.yaml
Example: Example:

38
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@ -0,0 +1,38 @@
DT compatible string versioning for SiFive open-source IP blocks
This document describes the version specification for DT "compatible"
strings for open-source SiFive IP blocks. HDL for these IP blocks
can be found in this public repository:
https://github.com/sifive/sifive-blocks
IP block-specific DT compatible strings are contained within the HDL,
in the form "sifive,<ip-block-name><integer version number>".
An example is "sifive,uart0" from:
https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
Until these IP blocks (or IP integration) support version
auto-discovery, the maintainers of these IP blocks intend to increment
the suffixed number in the compatible string whenever the software
interface to these IP blocks changes, or when the functionality of the
underlying IP blocks changes in a way that software should be aware of.
Driver developers can use compatible string "match" values such as
"sifive,uart0" to indicate that their driver is compatible with the
register interface and functionality associated with the relevant
upstream sifive-blocks commits. It is expected that most drivers will
match on these IP block-specific compatible strings.
DT data authors, when writing data for a particular SoC, should
continue to specify an SoC-specific compatible string value, such as
"sifive,fu540-c000-uart". This way, if SoC-specific
integration-specific bug fixes or workarounds are needed, the kernel
or other system software can match on this string to apply them. The
IP block-specific compatible string (such as "sifive,uart0") should
then be specified as a subsequent value.
An example of this style:
compatible = "sifive,fu540-c000-uart", "sifive,uart0";

2
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@ -251,7 +251,7 @@ for defining a counter device.
.. kernel-doc:: include/linux/counter.h .. kernel-doc:: include/linux/counter.h
:internal: :internal:
.. kernel-doc:: drivers/counter/generic-counter.c .. kernel-doc:: drivers/counter/counter.c
:export: :export:
Implementation Implementation

2
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@ -423,7 +423,7 @@ will be enumerated to depends on the device ID returned by _HID.
For example, the following ACPI sample might be used to enumerate an lm75-type For example, the following ACPI sample might be used to enumerate an lm75-type
I2C temperature sensor and match it to the driver using the Device Tree I2C temperature sensor and match it to the driver using the Device Tree
namespace link: namespace link::
Device (TMP0) Device (TMP0)
{ {

2
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@ -410,7 +410,7 @@ Notes on loading the dump-capture kernel:
* Boot parameter "1" boots the dump-capture kernel into single-user * Boot parameter "1" boots the dump-capture kernel into single-user
mode without networking. If you want networking, use "3". mode without networking. If you want networking, use "3".
* We generally don' have to bring up a SMP kernel just to capture the * We generally don't have to bring up a SMP kernel just to capture the
dump. Hence generally it is useful either to build a UP dump-capture dump. Hence generally it is useful either to build a UP dump-capture
kernel or specify maxcpus=1 option while loading dump-capture kernel. kernel or specify maxcpus=1 option while loading dump-capture kernel.
Note, though maxcpus always works, you had better replace it with Note, though maxcpus always works, you had better replace it with

30
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@ -0,0 +1,30 @@
.. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
Vendor Device Drivers
=====================
Contents:
.. toctree::
:maxdepth: 2
freescale/dpaa2/index
intel/e100
intel/e1000
intel/e1000e
intel/fm10k
intel/igb
intel/igbvf
intel/ixgb
intel/ixgbe
intel/ixgbevf
intel/i40e
intel/iavf
intel/ice
.. only:: subproject
Indices
=======
* :ref:`genindex`

16
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@ -11,19 +11,7 @@ Contents:
batman-adv batman-adv
can can
can_ucan_protocol can_ucan_protocol
device_drivers/freescale/dpaa2/index device_drivers/index
device_drivers/intel/e100
device_drivers/intel/e1000
device_drivers/intel/e1000e
device_drivers/intel/fm10k
device_drivers/intel/igb
device_drivers/intel/igbvf
device_drivers/intel/ixgb
device_drivers/intel/ixgbe
device_drivers/intel/ixgbevf
device_drivers/intel/i40e
device_drivers/intel/iavf
device_drivers/intel/ice
dsa/index dsa/index
devlink-info-versions devlink-info-versions
ieee802154 ieee802154
@ -40,6 +28,8 @@ Contents:
checksum-offloads checksum-offloads
segmentation-offloads segmentation-offloads
scaling scaling
tls
tls-offload
.. only:: subproject .. only:: subproject

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@ -0,0 +1,482 @@
.. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
==================
Kernel TLS offload
==================
Kernel TLS operation
====================
Linux kernel provides TLS connection offload infrastructure. Once a TCP
connection is in ``ESTABLISHED`` state user space can enable the TLS Upper
Layer Protocol (ULP) and install the cryptographic connection state.
For details regarding the user-facing interface refer to the TLS
documentation in :ref:`Documentation/networking/tls.rst <kernel_tls>`.
``ktls`` can operate in three modes:
* Software crypto mode (``TLS_SW``) - CPU handles the cryptography.
In most basic cases only crypto operations synchronous with the CPU
can be used, but depending on calling context CPU may utilize
asynchronous crypto accelerators. The use of accelerators introduces extra
latency on socket reads (decryption only starts when a read syscall
is made) and additional I/O load on the system.
* Packet-based NIC offload mode (``TLS_HW``) - the NIC handles crypto
on a packet by packet basis, provided the packets arrive in order.
This mode integrates best with the kernel stack and is described in detail
in the remaining part of this document
(``ethtool`` flags ``tls-hw-tx-offload`` and ``tls-hw-rx-offload``).
* Full TCP NIC offload mode (``TLS_HW_RECORD``) - mode of operation where
NIC driver and firmware replace the kernel networking stack
with its own TCP handling, it is not usable in production environments
making use of the Linux networking stack for example any firewalling
abilities or QoS and packet scheduling (``ethtool`` flag ``tls-hw-record``).
The operation mode is selected automatically based on device configuration,
offload opt-in or opt-out on per-connection basis is not currently supported.
TX
--
At a high level user write requests are turned into a scatter list, the TLS ULP
intercepts them, inserts record framing, performs encryption (in ``TLS_SW``
mode) and then hands the modified scatter list to the TCP layer. From this
point on the TCP stack proceeds as normal.
In ``TLS_HW`` mode the encryption is not performed in the TLS ULP.
Instead packets reach a device driver, the driver will mark the packets
for crypto offload based on the socket the packet is attached to,
and send them to the device for encryption and transmission.
RX
--
On the receive side if the device handled decryption and authentication
successfully, the driver will set the decrypted bit in the associated
:c:type:`struct sk_buff <sk_buff>`. The packets reach the TCP stack and
are handled normally. ``ktls`` is informed when data is queued to the socket
and the ``strparser`` mechanism is used to delineate the records. Upon read
request, records are retrieved from the socket and passed to decryption routine.
If device decrypted all the segments of the record the decryption is skipped,
otherwise software path handles decryption.
.. kernel-figure:: tls-offload-layers.svg
:alt: TLS offload layers
:align: center
:figwidth: 28em
Layers of Kernel TLS stack
Device configuration
====================
During driver initialization device sets the ``NETIF_F_HW_TLS_RX`` and
``NETIF_F_HW_TLS_TX`` features and installs its
:c:type:`struct tlsdev_ops <tlsdev_ops>`
pointer in the :c:member:`tlsdev_ops` member of the
:c:type:`struct net_device <net_device>`.
When TLS cryptographic connection state is installed on a ``ktls`` socket
(note that it is done twice, once for RX and once for TX direction,
and the two are completely independent), the kernel checks if the underlying
network device is offload-capable and attempts the offload. In case offload
fails the connection is handled entirely in software using the same mechanism
as if the offload was never tried.
Offload request is performed via the :c:member:`tls_dev_add` callback of
:c:type:`struct tlsdev_ops <tlsdev_ops>`:
.. code-block:: c
int (*tls_dev_add)(struct net_device *netdev, struct sock *sk,
enum tls_offload_ctx_dir direction,
struct tls_crypto_info *crypto_info,
u32 start_offload_tcp_sn);
``direction`` indicates whether the cryptographic information is for
the received or transmitted packets. Driver uses the ``sk`` parameter
to retrieve the connection 5-tuple and socket family (IPv4 vs IPv6).
Cryptographic information in ``crypto_info`` includes the key, iv, salt
as well as TLS record sequence number. ``start_offload_tcp_sn`` indicates
which TCP sequence number corresponds to the beginning of the record with
sequence number from ``crypto_info``. The driver can add its state
at the end of kernel structures (see :c:member:`driver_state` members
in ``include/net/tls.h``) to avoid additional allocations and pointer
dereferences.
TX
--
After TX state is installed, the stack guarantees that the first segment
of the stream will start exactly at the ``start_offload_tcp_sn`` sequence
number, simplifying TCP sequence number matching.
TX offload being fully initialized does not imply that all segments passing
through the driver and which belong to the offloaded socket will be after
the expected sequence number and will have kernel record information.
In particular, already encrypted data may have been queued to the socket
before installing the connection state in the kernel.
RX
--
In RX direction local networking stack has little control over the segmentation,
so the initial records' TCP sequence number may be anywhere inside the segment.
Normal operation
================
At the minimum the device maintains the following state for each connection, in
each direction:
* crypto secrets (key, iv, salt)
* crypto processing state (partial blocks, partial authentication tag, etc.)
* record metadata (sequence number, processing offset and length)
* expected TCP sequence number
There are no guarantees on record length or record segmentation. In particular
segments may start at any point of a record and contain any number of records.
Assuming segments are received in order, the device should be able to perform
crypto operations and authentication regardless of segmentation. For this
to be possible device has to keep small amount of segment-to-segment state.
This includes at least:
* partial headers (if a segment carried only a part of the TLS header)
* partial data block
* partial authentication tag (all data had been seen but part of the
authentication tag has to be written or read from the subsequent segment)
Record reassembly is not necessary for TLS offload. If the packets arrive
in order the device should be able to handle them separately and make
forward progress.
TX
--
The kernel stack performs record framing reserving space for the authentication
tag and populating all other TLS header and tailer fields.
Both the device and the driver maintain expected TCP sequence numbers
due to the possibility of retransmissions and the lack of software fallback
once the packet reaches the device.
For segments passed in order, the driver marks the packets with
a connection identifier (note that a 5-tuple lookup is insufficient to identify
packets requiring HW offload, see the :ref:`5tuple_problems` section)
and hands them to the device. The device identifies the packet as requiring
TLS handling and confirms the sequence number matches its expectation.
The device performs encryption and authentication of the record data.
It replaces the authentication tag and TCP checksum with correct values.
RX
--
Before a packet is DMAed to the host (but after NIC's embedded switching
and packet transformation functions) the device validates the Layer 4
checksum and performs a 5-tuple lookup to find any TLS connection the packet
may belong to (technically a 4-tuple
lookup is sufficient - IP addresses and TCP port numbers, as the protocol
is always TCP). If connection is matched device confirms if the TCP sequence
number is the expected one and proceeds to TLS handling (record delineation,
decryption, authentication for each record in the packet). The device leaves
the record framing unmodified, the stack takes care of record decapsulation.
Device indicates successful handling of TLS offload in the per-packet context
(descriptor) passed to the host.
Upon reception of a TLS offloaded packet, the driver sets
the :c:member:`decrypted` mark in :c:type:`struct sk_buff <sk_buff>`
corresponding to the segment. Networking stack makes sure decrypted
and non-decrypted segments do not get coalesced (e.g. by GRO or socket layer)
and takes care of partial decryption.
Resync handling
===============
In presence of packet drops or network packet reordering, the device may lose
synchronization with the TLS stream, and require a resync with the kernel's
TCP stack.
Note that resync is only attempted for connections which were successfully
added to the device table and are in TLS_HW mode. For example,
if the table was full when cryptographic state was installed in the kernel,
such connection will never get offloaded. Therefore the resync request
does not carry any cryptographic connection state.
TX
--
Segments transmitted from an offloaded socket can get out of sync
in similar ways to the receive side-retransmissions - local drops
are possible, though network reorders are not.
Whenever an out of order segment is transmitted the driver provides
the device with enough information to perform cryptographic operations.
This means most likely that the part of the record preceding the current
segment has to be passed to the device as part of the packet context,
together with its TCP sequence number and TLS record number. The device
can then initialize its crypto state, process and discard the preceding
data (to be able to insert the authentication tag) and move onto handling
the actual packet.
In this mode depending on the implementation the driver can either ask
for a continuation with the crypto state and the new sequence number
(next expected segment is the one after the out of order one), or continue
with the previous stream state - assuming that the out of order segment
was just a retransmission. The former is simpler, and does not require
retransmission detection therefore it is the recommended method until
such time it is proven inefficient.
RX
--
A small amount of RX reorder events may not require a full resynchronization.
In particular the device should not lose synchronization
when record boundary can be recovered:
.. kernel-figure:: tls-offload-reorder-good.svg
:alt: reorder of non-header segment
:align: center
Reorder of non-header segment
Green segments are successfully decrypted, blue ones are passed
as received on wire, red stripes mark start of new records.
In above case segment 1 is received and decrypted successfully.
Segment 2 was dropped so 3 arrives out of order. The device knows
the next record starts inside 3, based on record length in segment 1.
Segment 3 is passed untouched, because due to lack of data from segment 2
the remainder of the previous record inside segment 3 cannot be handled.
The device can, however, collect the authentication algorithm's state
and partial block from the new record in segment 3 and when 4 and 5
arrive continue decryption. Finally when 2 arrives it's completely outside
of expected window of the device so it's passed as is without special
handling. ``ktls`` software fallback handles the decryption of record
spanning segments 1, 2 and 3. The device did not get out of sync,
even though two segments did not get decrypted.
Kernel synchronization may be necessary if the lost segment contained
a record header and arrived after the next record header has already passed:
.. kernel-figure:: tls-offload-reorder-bad.svg
:alt: reorder of header segment
:align: center
Reorder of segment with a TLS header
In this example segment 2 gets dropped, and it contains a record header.
Device can only detect that segment 4 also contains a TLS header
if it knows the length of the previous record from segment 2. In this case
the device will lose synchronization with the stream.
When the device gets out of sync and the stream reaches TCP sequence
numbers more than a max size record past the expected TCP sequence number,
the device starts scanning for a known header pattern. For example
for TLS 1.2 and TLS 1.3 subsequent bytes of value ``0x03 0x03`` occur
in the SSL/TLS version field of the header. Once pattern is matched
the device continues attempting parsing headers at expected locations
(based on the length fields at guessed locations).
Whenever the expected location does not contain a valid header the scan
is restarted.
When the header is matched the device sends a confirmation request
to the kernel, asking if the guessed location is correct (if a TLS record
really starts there), and which record sequence number the given header had.
The kernel confirms the guessed location was correct and tells the device
the record sequence number. Meanwhile, the device had been parsing
and counting all records since the just-confirmed one, it adds the number
of records it had seen to the record number provided by the kernel.
At this point the device is in sync and can resume decryption at next
segment boundary.
In a pathological case the device may latch onto a sequence of matching
headers and never hear back from the kernel (there is no negative
confirmation from the kernel). The implementation may choose to periodically
restart scan. Given how unlikely falsely-matching stream is, however,
periodic restart is not deemed necessary.
Special care has to be taken if the confirmation request is passed
asynchronously to the packet stream and record may get processed
by the kernel before the confirmation request.
Error handling
==============
TX
--
Packets may be redirected or rerouted by the stack to a different
device than the selected TLS offload device. The stack will handle
such condition using the :c:func:`sk_validate_xmit_skb` helper
(TLS offload code installs :c:func:`tls_validate_xmit_skb` at this hook).
Offload maintains information about all records until the data is
fully acknowledged, so if skbs reach the wrong device they can be handled
by software fallback.
Any device TLS offload handling error on the transmission side must result
in the packet being dropped. For example if a packet got out of order
due to a bug in the stack or the device, reached the device and can't
be encrypted such packet must be dropped.
RX
--
If the device encounters any problems with TLS offload on the receive
side it should pass the packet to the host's networking stack as it was
received on the wire.
For example authentication failure for any record in the segment should
result in passing the unmodified packet to the software fallback. This means
packets should not be modified "in place". Splitting segments to handle partial
decryption is not advised. In other words either all records in the packet
had been handled successfully and authenticated or the packet has to be passed
to the host's stack as it was on the wire (recovering original packet in the
driver if device provides precise error is sufficient).
The Linux networking stack does not provide a way of reporting per-packet
decryption and authentication errors, packets with errors must simply not
have the :c:member:`decrypted` mark set.
A packet should also not be handled by the TLS offload if it contains
incorrect checksums.
Performance metrics
===================
TLS offload can be characterized by the following basic metrics:
* max connection count
* connection installation rate
* connection installation latency
* total cryptographic performance
Note that each TCP connection requires a TLS session in both directions,
the performance may be reported treating each direction separately.
Max connection count
--------------------
The number of connections device can support can be exposed via
``devlink resource`` API.
Total cryptographic performance
-------------------------------
Offload performance may depend on segment and record size.
Overload of the cryptographic subsystem of the device should not have
significant performance impact on non-offloaded streams.
Statistics
==========
Following minimum set of TLS-related statistics should be reported
by the driver:
* ``rx_tls_decrypted`` - number of successfully decrypted TLS segments
* ``tx_tls_encrypted`` - number of in-order TLS segments passed to device
for encryption
* ``tx_tls_ooo`` - number of TX packets which were part of a TLS stream
but did not arrive in the expected order
* ``tx_tls_drop_no_sync_data`` - number of TX packets dropped because
they arrived out of order and associated record could not be found
(see also :ref:`pre_tls_data`)
Notable corner cases, exceptions and additional requirements
============================================================
.. _5tuple_problems:
5-tuple matching limitations
----------------------------
The device can only recognize received packets based on the 5-tuple
of the socket. Current ``ktls`` implementation will not offload sockets
routed through software interfaces such as those used for tunneling
or virtual networking. However, many packet transformations performed
by the networking stack (most notably any BPF logic) do not require
any intermediate software device, therefore a 5-tuple match may
consistently miss at the device level. In such cases the device
should still be able to perform TX offload (encryption) and should
fallback cleanly to software decryption (RX).
Out of order
------------
Introducing extra processing in NICs should not cause packets to be
transmitted or received out of order, for example pure ACK packets
should not be reordered with respect to data segments.
Ingress reorder
---------------
A device is permitted to perform packet reordering for consecutive
TCP segments (i.e. placing packets in the correct order) but any form
of additional buffering is disallowed.
Coexistence with standard networking offload features
-----------------------------------------------------
Offloaded ``ktls`` sockets should support standard TCP stack features
transparently. Enabling device TLS offload should not cause any difference
in packets as seen on the wire.
Transport layer transparency
----------------------------
The device should not modify any packet headers for the purpose
of the simplifying TLS offload.
The device should not depend on any packet headers beyond what is strictly
necessary for TLS offload.
Segment drops
-------------
Dropping packets is acceptable only in the event of catastrophic
system errors and should never be used as an error handling mechanism
in cases arising from normal operation. In other words, reliance
on TCP retransmissions to handle corner cases is not acceptable.
TLS device features
-------------------
Drivers should ignore the changes to TLS the device feature flags.
These flags will be acted upon accordingly by the core ``ktls`` code.
TLS device feature flags only control adding of new TLS connection
offloads, old connections will remain active after flags are cleared.
Known bugs
==========
skb_orphan() leaks clear text
-----------------------------
Currently drivers depend on the :c:member:`sk` member of
:c:type:`struct sk_buff <sk_buff>` to identify segments requiring
encryption. Any operation which removes or does not preserve the socket
association such as :c:func:`skb_orphan` or :c:func:`skb_clone`
will cause the driver to miss the packets and lead to clear text leaks.
Redirects leak clear text
-------------------------
In the RX direction, if segment has already been decrypted by the device
and it gets redirected or mirrored - clear text will be transmitted out.
.. _pre_tls_data:
Transmission of pre-TLS data
----------------------------
User can enqueue some already encrypted and framed records before enabling
``ktls`` on the socket. Those records have to get sent as they are. This is
perfectly easy to handle in the software case - such data will be waiting
in the TCP layer, TLS ULP won't see it. In the offloaded case when pre-queued
segment reaches transmission point it appears to be out of order (before the
expected TCP sequence number) and the stack does not have a record information
associated.
All segments without record information cannot, however, be assumed to be
pre-queued data, because a race condition exists between TCP stack queuing
a retransmission, the driver seeing the retransmission and TCP ACK arriving
for the retransmitted data.

44
Documentation/networking/tls.txt → Documentation/networking/tls.rst
View File

@ -1,3 +1,9 @@
.. _kernel_tls:
==========
Kernel TLS
==========
Overview Overview
======== ========
@ -12,6 +18,8 @@ Creating a TLS connection
First create a new TCP socket and set the TLS ULP. First create a new TCP socket and set the TLS ULP.
.. code-block:: c
sock = socket(AF_INET, SOCK_STREAM, 0); sock = socket(AF_INET, SOCK_STREAM, 0);
setsockopt(sock, SOL_TCP, TCP_ULP, "tls", sizeof("tls")); setsockopt(sock, SOL_TCP, TCP_ULP, "tls", sizeof("tls"));
@ -21,6 +29,8 @@ handshake is complete, we have all the parameters required to move the
data-path to the kernel. There is a separate socket option for moving data-path to the kernel. There is a separate socket option for moving
the transmit and the receive into the kernel. the transmit and the receive into the kernel.
.. code-block:: c
/* From linux/tls.h */ /* From linux/tls.h */
struct tls_crypto_info { struct tls_crypto_info {
unsigned short version; unsigned short version;
@ -58,6 +68,8 @@ After setting the TLS_TX socket option all application data sent over this
socket is encrypted using TLS and the parameters provided in the socket option. socket is encrypted using TLS and the parameters provided in the socket option.
For example, we can send an encrypted hello world record as follows: For example, we can send an encrypted hello world record as follows:
.. code-block:: c
const char *msg = "hello world\n"; const char *msg = "hello world\n";
send(sock, msg, strlen(msg)); send(sock, msg, strlen(msg));
@ -67,6 +79,8 @@ to the encrypted kernel send buffer if possible.
The sendfile system call will send the file's data over TLS records of maximum The sendfile system call will send the file's data over TLS records of maximum
length (2^14). length (2^14).
.. code-block:: c
file = open(filename, O_RDONLY); file = open(filename, O_RDONLY);
fstat(file, &stat); fstat(file, &stat);
sendfile(sock, file, &offset, stat.st_size); sendfile(sock, file, &offset, stat.st_size);
@ -89,6 +103,8 @@ After setting the TLS_RX socket option, all recv family socket calls
are decrypted using TLS parameters provided. A full TLS record must are decrypted using TLS parameters provided. A full TLS record must
be received before decryption can happen. be received before decryption can happen.
.. code-block:: c
char buffer[16384]; char buffer[16384];
recv(sock, buffer, 16384); recv(sock, buffer, 16384);
@ -97,12 +113,12 @@ large enough, and no additional allocations occur. If the userspace
buffer is too small, data is decrypted in the kernel and copied to buffer is too small, data is decrypted in the kernel and copied to
userspace. userspace.
EINVAL is returned if the TLS version in the received message does not ``EINVAL`` is returned if the TLS version in the received message does not
match the version passed in setsockopt. match the version passed in setsockopt.
EMSGSIZE is returned if the received message is too big. ``EMSGSIZE`` is returned if the received message is too big.
EBADMSG is returned if decryption failed for any other reason. ``EBADMSG`` is returned if decryption failed for any other reason.
Send TLS control messages Send TLS control messages
------------------------- -------------------------
@ -113,9 +129,11 @@ These messages can be sent over the socket by providing the TLS record type
via a CMSG. For example the following function sends @data of @length bytes via a CMSG. For example the following function sends @data of @length bytes
using a record of type @record_type. using a record of type @record_type.
/* send TLS control message using record_type */ .. code-block:: c
/* send TLS control message using record_type */
static int klts_send_ctrl_message(int sock, unsigned char record_type, static int klts_send_ctrl_message(int sock, unsigned char record_type,
void *data, size_t length) void *data, size_t length)
{ {
struct msghdr msg = {0}; struct msghdr msg = {0};
int cmsg_len = sizeof(record_type); int cmsg_len = sizeof(record_type);
@ -151,6 +169,8 @@ type passed via cmsg. If no cmsg buffer is provided, an error is
returned if a control message is received. Data messages may be returned if a control message is received. Data messages may be
received without a cmsg buffer set. received without a cmsg buffer set.
.. code-block:: c
char buffer[16384]; char buffer[16384];
char cmsg[CMSG_SPACE(sizeof(unsigned char))]; char cmsg[CMSG_SPACE(sizeof(unsigned char))];
struct msghdr msg = {0}; struct msghdr msg = {0};
@ -186,12 +206,10 @@ Integrating in to userspace TLS library
At a high level, the kernel TLS ULP is a replacement for the record At a high level, the kernel TLS ULP is a replacement for the record
layer of a userspace TLS library. layer of a userspace TLS library.
A patchset to OpenSSL to use ktls as the record layer is here: A patchset to OpenSSL to use ktls as the record layer is
`here <https://github.com/Mellanox/openssl/commits/tls_rx2>`_.
https://github.com/Mellanox/openssl/commits/tls_rx2 `An example <https://github.com/ktls/af_ktls-tool/commits/RX>`_
of calling send directly after a handshake using gnutls.
An example of calling send directly after a handshake using Since it doesn't implement a full record layer, control
gnutls. Since it doesn't implement a full record layer, control messages are not supported.
messages are not supported:
https://github.com/ktls/af_ktls-tool/commits/RX

44
Documentation/sphinx/kerneldoc.py
View File

@ -37,7 +37,19 @@ import glob
from docutils import nodes, statemachine from docutils import nodes, statemachine
from docutils.statemachine import ViewList from docutils.statemachine import ViewList
from docutils.parsers.rst import directives, Directive from docutils.parsers.rst import directives, Directive
from sphinx.ext.autodoc import AutodocReporter
#
# AutodocReporter is only good up to Sphinx 1.7
#
import sphinx
Use_SSI = sphinx.__version__[:3] >= '1.7'
if Use_SSI:
from sphinx.util.docutils import switch_source_input
else:
from sphinx.ext.autodoc import AutodocReporter
import kernellog
__version__ = '1.0' __version__ = '1.0'
@ -90,7 +102,8 @@ class KernelDocDirective(Directive):
cmd += [filename] cmd += [filename]
try: try:
env.app.verbose('calling kernel-doc \'%s\'' % (" ".join(cmd))) kernellog.verbose(env.app,
'calling kernel-doc \'%s\'' % (" ".join(cmd)))
p = subprocess.Popen(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE) p = subprocess.Popen(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
out, err = p.communicate() out, err = p.communicate()
@ -100,7 +113,8 @@ class KernelDocDirective(Directive):
if p.returncode != 0: if p.returncode != 0:
sys.stderr.write(err) sys.stderr.write(err)
env.app.warn('kernel-doc \'%s\' failed with return code %d' % (" ".join(cmd), p.returncode)) kernellog.warn(env.app,
'kernel-doc \'%s\' failed with return code %d' % (" ".join(cmd), p.returncode))
return [nodes.error(None, nodes.paragraph(text = "kernel-doc missing"))] return [nodes.error(None, nodes.paragraph(text = "kernel-doc missing"))]
elif env.config.kerneldoc_verbosity > 0: elif env.config.kerneldoc_verbosity > 0:
sys.stderr.write(err) sys.stderr.write(err)
@ -121,20 +135,28 @@ class KernelDocDirective(Directive):
lineoffset += 1 lineoffset += 1
node = nodes.section() node = nodes.section()
buf = self.state.memo.title_styles, self.state.memo.section_level, self.state.memo.reporter self.do_parse(result, node)
return node.children
except Exception as e: # pylint: disable=W0703
kernellog.warn(env.app, 'kernel-doc \'%s\' processing failed with: %s' %
(" ".join(cmd), str(e)))
return [nodes.error(None, nodes.paragraph(text = "kernel-doc missing"))]
def do_parse(self, result, node):
if Use_SSI:
with switch_source_input(self.state, result):
self.state.nested_parse(result, 0, node, match_titles=1)
else:
save = self.state.memo.title_styles, self.state.memo.section_level, self.state.memo.reporter
self.state.memo.reporter = AutodocReporter(result, self.state.memo.reporter) self.state.memo.reporter = AutodocReporter(result, self.state.memo.reporter)
self.state.memo.title_styles, self.state.memo.section_level = [], 0 self.state.memo.title_styles, self.state.memo.section_level = [], 0
try: try:
self.state.nested_parse(result, 0, node, match_titles=1) self.state.nested_parse(result, 0, node, match_titles=1)
finally: finally:
self.state.memo.title_styles, self.state.memo.section_level, self.state.memo.reporter = buf self.state.memo.title_styles, self.state.memo.section_level, self.state.memo.reporter = save
return node.children
except Exception as e: # pylint: disable=W0703
env.app.warn('kernel-doc \'%s\' processing failed with: %s' %
(" ".join(cmd), str(e)))
return [nodes.error(None, nodes.paragraph(text = "kernel-doc missing"))]
def setup(app): def setup(app):
app.add_config_value('kerneldoc_bin', None, 'env') app.add_config_value('kerneldoc_bin', None, 'env')

28
Documentation/sphinx/kernellog.py Normal file
View File

@ -0,0 +1,28 @@
# SPDX-License-Identifier: GPL-2.0
#
# Sphinx has deprecated its older logging interface, but the replacement
# only goes back to 1.6. So here's a wrapper layer to keep around for
# as long as we support 1.4.
#
import sphinx
if sphinx.__version__[:3] >= '1.6':
UseLogging = True
from sphinx.util import logging
logger = logging.getLogger('kerneldoc')
else:
UseLogging = False
def warn(app, message):
if UseLogging:
logger.warning(message)
else:
app.warn(message)
def verbose(app, message):
if UseLogging:
logger.verbose(message)
else:
app.verbose(message)

40
Documentation/sphinx/kfigure.py
View File

@ -60,6 +60,8 @@ import sphinx
from sphinx.util.nodes import clean_astext from sphinx.util.nodes import clean_astext
from six import iteritems from six import iteritems
import kernellog
PY3 = sys.version_info[0] == 3 PY3 = sys.version_info[0] == 3
if PY3: if PY3:
@ -171,20 +173,20 @@ def setupTools(app):
This function is called once, when the builder is initiated. This function is called once, when the builder is initiated.
""" """
global dot_cmd, convert_cmd # pylint: disable=W0603 global dot_cmd, convert_cmd # pylint: disable=W0603
app.verbose("kfigure: check installed tools ...") kernellog.verbose(app, "kfigure: check installed tools ...")
dot_cmd = which('dot') dot_cmd = which('dot')
convert_cmd = which('convert') convert_cmd = which('convert')
if dot_cmd: if dot_cmd:
app.verbose("use dot(1) from: " + dot_cmd) kernellog.verbose(app, "use dot(1) from: " + dot_cmd)
else: else:
app.warn("dot(1) not found, for better output quality install " kernellog.warn(app, "dot(1) not found, for better output quality install "
"graphviz from http://www.graphviz.org") "graphviz from http://www.graphviz.org")
if convert_cmd: if convert_cmd:
app.verbose("use convert(1) from: " + convert_cmd) kernellog.verbose(app, "use convert(1) from: " + convert_cmd)
else: else:
app.warn( kernellog.warn(app,
"convert(1) not found, for SVG to PDF conversion install " "convert(1) not found, for SVG to PDF conversion install "
"ImageMagick (https://www.imagemagick.org)") "ImageMagick (https://www.imagemagick.org)")
@ -220,12 +222,13 @@ def convert_image(img_node, translator, src_fname=None):
# in kernel builds, use 'make SPHINXOPTS=-v' to see verbose messages # in kernel builds, use 'make SPHINXOPTS=-v' to see verbose messages
app.verbose('assert best format for: ' + img_node['uri']) kernellog.verbose(app, 'assert best format for: ' + img_node['uri'])
if in_ext == '.dot': if in_ext == '.dot':
if not dot_cmd: if not dot_cmd:
app.verbose("dot from graphviz not available / include DOT raw.") kernellog.verbose(app,
"dot from graphviz not available / include DOT raw.")
img_node.replace_self(file2literal(src_fname)) img_node.replace_self(file2literal(src_fname))
elif translator.builder.format == 'latex': elif translator.builder.format == 'latex':
@ -252,7 +255,8 @@ def convert_image(img_node, translator, src_fname=None):
if translator.builder.format == 'latex': if translator.builder.format == 'latex':
if convert_cmd is None: if convert_cmd is None:
app.verbose("no SVG to PDF conversion available / include SVG raw.") kernellog.verbose(app,
"no SVG to PDF conversion available / include SVG raw.")
img_node.replace_self(file2literal(src_fname)) img_node.replace_self(file2literal(src_fname))
else: else:
dst_fname = path.join(translator.builder.outdir, fname + '.pdf') dst_fname = path.join(translator.builder.outdir, fname + '.pdf')
@ -265,18 +269,19 @@ def convert_image(img_node, translator, src_fname=None):
_name = dst_fname[len(translator.builder.outdir) + 1:] _name = dst_fname[len(translator.builder.outdir) + 1:]
if isNewer(dst_fname, src_fname): if isNewer(dst_fname, src_fname):
app.verbose("convert: {out}/%s already exists and is newer" % _name) kernellog.verbose(app,
"convert: {out}/%s already exists and is newer" % _name)
else: else:
ok = False ok = False
mkdir(path.dirname(dst_fname)) mkdir(path.dirname(dst_fname))
if in_ext == '.dot': if in_ext == '.dot':
app.verbose('convert DOT to: {out}/' + _name) kernellog.verbose(app, 'convert DOT to: {out}/' + _name)
ok = dot2format(app, src_fname, dst_fname) ok = dot2format(app, src_fname, dst_fname)
elif in_ext == '.svg': elif in_ext == '.svg':
app.verbose('convert SVG to: {out}/' + _name) kernellog.verbose(app, 'convert SVG to: {out}/' + _name)
ok = svg2pdf(app, src_fname, dst_fname) ok = svg2pdf(app, src_fname, dst_fname)
if not ok: if not ok:
@ -305,7 +310,8 @@ def dot2format(app, dot_fname, out_fname):
with open(out_fname, "w") as out: with open(out_fname, "w") as out:
exit_code = subprocess.call(cmd, stdout = out) exit_code = subprocess.call(cmd, stdout = out)
if exit_code != 0: if exit_code != 0:
app.warn("Error #%d when calling: %s" % (exit_code, " ".join(cmd))) kernellog.warn(app,
"Error #%d when calling: %s" % (exit_code, " ".join(cmd)))
return bool(exit_code == 0) return bool(exit_code == 0)
def svg2pdf(app, svg_fname, pdf_fname): def svg2pdf(app, svg_fname, pdf_fname):
@ -322,7 +328,7 @@ def svg2pdf(app, svg_fname, pdf_fname):
# use stdout and stderr from parent # use stdout and stderr from parent
exit_code = subprocess.call(cmd) exit_code = subprocess.call(cmd)
if exit_code != 0: if exit_code != 0:
app.warn("Error #%d when calling: %s" % (exit_code, " ".join(cmd))) kernellog.warn(app, "Error #%d when calling: %s" % (exit_code, " ".join(cmd)))
return bool(exit_code == 0) return bool(exit_code == 0)
@ -415,15 +421,15 @@ def visit_kernel_render(self, node):
app = self.builder.app app = self.builder.app
srclang = node.get('srclang') srclang = node.get('srclang')
app.verbose('visit kernel-render node lang: "%s"' % (srclang)) kernellog.verbose(app, 'visit kernel-render node lang: "%s"' % (srclang))
tmp_ext = RENDER_MARKUP_EXT.get(srclang, None) tmp_ext = RENDER_MARKUP_EXT.get(srclang, None)
if tmp_ext is None: if tmp_ext is None:
app.warn('kernel-render: "%s" unknown / include raw.' % (srclang)) kernellog.warn(app, 'kernel-render: "%s" unknown / include raw.' % (srclang))
return return
if not dot_cmd and tmp_ext == '.dot': if not dot_cmd and tmp_ext == '.dot':
app.verbose("dot from graphviz not available / include raw.") kernellog.verbose(app, "dot from graphviz not available / include raw.")
return return
literal_block = node[0] literal_block = node[0]

10
MAINTAINERS
View File

@ -2627,7 +2627,7 @@ F: Documentation/devicetree/bindings/eeprom/at24.txt
F: drivers/misc/eeprom/at24.c F: drivers/misc/eeprom/at24.c
ATA OVER ETHERNET (AOE) DRIVER ATA OVER ETHERNET (AOE) DRIVER
M: "Ed L. Cashin" <ed.cashin@acm.org> M: "Justin Sanders" <justin@coraid.com>
W: http://www.openaoe.org/ W: http://www.openaoe.org/
S: Supported S: Supported
F: Documentation/aoe/ F: Documentation/aoe/
@ -2768,7 +2768,7 @@ AVIA HX711 ANALOG DIGITAL CONVERTER IIO DRIVER
M: Andreas Klinger <ak@it-klinger.de> M: Andreas Klinger <ak@it-klinger.de>
L: linux-iio@vger.kernel.org L: linux-iio@vger.kernel.org
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/iio/adc/avia-hx711.txt F: Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml
F: drivers/iio/adc/hx711.c F: drivers/iio/adc/hx711.c
AX.25 NETWORK LAYER AX.25 NETWORK LAYER
@ -8611,14 +8611,12 @@ F: arch/x86/include/asm/svm.h
F: arch/x86/kvm/svm.c F: arch/x86/kvm/svm.c
KERNEL VIRTUAL MACHINE FOR ARM/ARM64 (KVM/arm, KVM/arm64) KERNEL VIRTUAL MACHINE FOR ARM/ARM64 (KVM/arm, KVM/arm64)
M: Christoffer Dall <christoffer.dall@arm.com>
M: Marc Zyngier <marc.zyngier@arm.com> M: Marc Zyngier <marc.zyngier@arm.com>
R: James Morse <james.morse@arm.com> R: James Morse <james.morse@arm.com>
R: Julien Thierry <julien.thierry@arm.com> R: Julien Thierry <julien.thierry@arm.com>
R: Suzuki K Pouloze <suzuki.poulose@arm.com> R: Suzuki K Pouloze <suzuki.poulose@arm.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: kvmarm@lists.cs.columbia.edu L: kvmarm@lists.cs.columbia.edu
W: http://systems.cs.columbia.edu/projects/kvm-arm
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git
S: Maintained S: Maintained
F: arch/arm/include/uapi/asm/kvm* F: arch/arm/include/uapi/asm/kvm*
@ -11226,7 +11224,7 @@ F: drivers/video/fbdev/riva/
F: drivers/video/fbdev/nvidia/ F: drivers/video/fbdev/nvidia/
NVM EXPRESS DRIVER NVM EXPRESS DRIVER
M: Keith Busch <keith.busch@intel.com> M: Keith Busch <kbusch@kernel.org>
M: Jens Axboe <axboe@fb.com> M: Jens Axboe <axboe@fb.com>
M: Christoph Hellwig <hch@lst.de> M: Christoph Hellwig <hch@lst.de>
M: Sagi Grimberg <sagi@grimberg.me> M: Sagi Grimberg <sagi@grimberg.me>
@ -14351,7 +14349,7 @@ SIMPLEFB FB DRIVER
M: Hans de Goede <hdegoede@redhat.com> M: Hans de Goede <hdegoede@redhat.com>
L: linux-fbdev@vger.kernel.org L: linux-fbdev@vger.kernel.org
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/display/simple-framebuffer.txt F: Documentation/devicetree/bindings/display/simple-framebuffer.yaml
F: drivers/video/fbdev/simplefb.c F: drivers/video/fbdev/simplefb.c
F: include/linux/platform_data/simplefb.h F: include/linux/platform_data/simplefb.h

4
Makefile
View File

@ -2,8 +2,8 @@
VERSION = 5 VERSION = 5
PATCHLEVEL = 2 PATCHLEVEL = 2
SUBLEVEL = 0 SUBLEVEL = 0
EXTRAVERSION = -rc1 EXTRAVERSION = -rc2
NAME = Shy Crocodile NAME = Golden Lions
# *DOCUMENTATION* # *DOCUMENTATION*
# To see a list of typical targets execute "make help" # To see a list of typical targets execute "make help"

10
arch/alpha/include/asm/xor.h
View File

@ -1,16 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
* include/asm-alpha/xor.h * include/asm-alpha/xor.h
* *
* Optimized RAID-5 checksumming functions for alpha EV5 and EV6 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* You should have received a copy of the GNU General Public License
* (for example /usr/src/linux/COPYING); if not, write to the Free
* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
extern void xor_alpha_2(unsigned long, unsigned long *, unsigned long *); extern void xor_alpha_2(unsigned long, unsigned long *, unsigned long *);

1
arch/arm/kvm/hyp/Makefile
View File

@ -11,6 +11,7 @@ CFLAGS_ARMV7VE :=$(call cc-option, -march=armv7ve)
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/aarch32.o
obj-$(CONFIG_KVM_ARM_HOST) += tlb.o obj-$(CONFIG_KVM_ARM_HOST) += tlb.o
obj-$(CONFIG_KVM_ARM_HOST) += cp15-sr.o obj-$(CONFIG_KVM_ARM_HOST) += cp15-sr.o

15
arch/arm/mach-davinci/board-sffsdr.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* Lyrtech SFFSDR board support. * Lyrtech SFFSDR board support.
* *
@ -7,20 +8,6 @@
* Based on DV-EVM platform, original copyright follows: * Based on DV-EVM platform, original copyright follows:
* *
* Copyright (C) 2007 MontaVista Software, Inc. * Copyright (C) 2007 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <linux/init.h> #include <linux/init.h>

16
arch/arm/mach-davinci/serial.c
View File

@ -1,22 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* TI DaVinci serial driver * TI DaVinci serial driver
* *
* Copyright (C) 2006 Texas Instruments. * Copyright (C) 2006 Texas Instruments.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>

15
arch/arm/mach-imx/iomux-v1.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* arch/arm/plat-mxc/iomux-v1.c * arch/arm/plat-mxc/iomux-v1.c
* *
@ -5,20 +6,6 @@
* Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix
* *
* Common code for i.MX1, i.MX21 and i.MX27 * Common code for i.MX1, i.MX21 and i.MX27
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/ */
#include <linux/errno.h> #include <linux/errno.h>

15
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
View File

@ -1,21 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
* PTP 1588 clock using the IXP46X * PTP 1588 clock using the IXP46X
* *
* Copyright (C) 2010 OMICRON electronics GmbH * Copyright (C) 2010 OMICRON electronics GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#ifndef _IXP46X_TS_H_ #ifndef _IXP46X_TS_H_

16
arch/arm/mach-omap2/omap_phy_internal.c
View File

@ -1,24 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* This file configures the internal USB PHY in OMAP4430. Used * This file configures the internal USB PHY in OMAP4430. Used
* with TWL6030 transceiver and MUSB on OMAP4430. * with TWL6030 transceiver and MUSB on OMAP4430.
* *
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Author: Hema HK <hemahk@ti.com> * Author: Hema HK <hemahk@ti.com>
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/ */
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

14
arch/arm/nwfpe/double_cpdo.c
View File

@ -1,22 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.COM, 1998,1999 (c) Rebel.COM, 1998,1999
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include "fpa11.h" #include "fpa11.h"

14
arch/arm/nwfpe/entry.S
View File

@ -1,3 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.COM, 1998 (c) Rebel.COM, 1998
@ -5,19 +6,6 @@
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <asm/assembler.h> #include <asm/assembler.h>
#include <asm/opcodes.h> #include <asm/opcodes.h>

14
arch/arm/nwfpe/extended_cpdo.c
View File

@ -1,22 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.COM, 1998,1999 (c) Rebel.COM, 1998,1999
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include "fpa11.h" #include "fpa11.h"

14
arch/arm/nwfpe/fpa11.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.COM, 1998,1999 (c) Rebel.COM, 1998,1999
@ -5,19 +6,6 @@
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include "fpa11.h" #include "fpa11.h"

14
arch/arm/nwfpe/fpa11.h
View File

@ -1,22 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.com, 1998-1999 (c) Rebel.com, 1998-1999
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#ifndef __FPA11_H__ #ifndef __FPA11_H__

14
arch/arm/nwfpe/fpa11_cpdo.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.COM, 1998,1999 (c) Rebel.COM, 1998,1999
@ -5,19 +6,6 @@
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include "fpa11.h" #include "fpa11.h"

14
arch/arm/nwfpe/fpa11_cpdt.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.com, 1998-1999 (c) Rebel.com, 1998-1999
@ -5,19 +6,6 @@
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include "fpa11.h" #include "fpa11.h"

14
arch/arm/nwfpe/fpa11_cprt.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.COM, 1998,1999 (c) Rebel.COM, 1998,1999
@ -5,19 +6,6 @@
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include "fpa11.h" #include "fpa11.h"

14
arch/arm/nwfpe/fpmodule.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
@ -6,19 +7,6 @@
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include "fpa11.h" #include "fpa11.h"

14
arch/arm/nwfpe/fpmodule.h
View File

@ -1,22 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.com, 1998-1999 (c) Rebel.com, 1998-1999
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27/03/03 Ian Molton Clean up CONFIG_CPU 27/03/03 Ian Molton Clean up CONFIG_CPU
*/ */

14
arch/arm/nwfpe/fpopcode.c
View File

@ -1,22 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.COM, 1998,1999 (c) Rebel.COM, 1998,1999
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include "fpa11.h" #include "fpa11.h"

14
arch/arm/nwfpe/fpopcode.h
View File

@ -1,3 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.COM, 1998,1999 (c) Rebel.COM, 1998,1999
@ -5,19 +6,6 @@
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#ifndef __FPOPCODE_H__ #ifndef __FPOPCODE_H__

14
arch/arm/nwfpe/fpsr.h
View File

@ -1,22 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.com, 1998-1999 (c) Rebel.com, 1998-1999
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#ifndef __FPSR_H__ #ifndef __FPSR_H__

14
arch/arm/nwfpe/single_cpdo.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
NetWinder Floating Point Emulator NetWinder Floating Point Emulator
(c) Rebel.COM, 1998,1999 (c) Rebel.COM, 1998,1999
@ -5,19 +6,6 @@
Direct questions, comments to Scott Bambrough <scottb@netwinder.org> Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include "fpa11.h" #include "fpa11.h"

26
arch/arm64/Kconfig
View File

@ -476,16 +476,15 @@ config ARM64_ERRATUM_1024718
If unsure, say Y. If unsure, say Y.
config ARM64_ERRATUM_1188873 config ARM64_ERRATUM_1418040
bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
default y default y
depends on COMPAT depends on COMPAT
select ARM_ARCH_TIMER_OOL_WORKAROUND
help help
This option adds a workaround for ARM Cortex-A76/Neoverse-N1 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
erratum 1188873. errata 1188873 and 1418040.
Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
cause register corruption when accessing the timer registers cause register corruption when accessing the timer registers
from AArch32 userspace. from AArch32 userspace.
@ -521,6 +520,24 @@ config ARM64_ERRATUM_1286807
If unsure, say Y. If unsure, say Y.
config ARM64_ERRATUM_1463225
bool "Cortex-A76: Software Step might prevent interrupt recognition"
default y
help
This option adds a workaround for Arm Cortex-A76 erratum 1463225.
On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
of a system call instruction (SVC) can prevent recognition of
subsequent interrupts when software stepping is disabled in the
exception handler of the system call and either kernel debugging
is enabled or VHE is in use.
Work around the erratum by triggering a dummy step exception
when handling a system call from a task that is being stepped
in a VHE configuration of the kernel.
If unsure, say Y.
config CAVIUM_ERRATUM_22375 config CAVIUM_ERRATUM_22375
bool "Cavium erratum 22375, 24313" bool "Cavium erratum 22375, 24313"
default y default y
@ -1406,6 +1423,7 @@ config ARM64_MODULE_PLTS
config ARM64_PSEUDO_NMI config ARM64_PSEUDO_NMI
bool "Support for NMI-like interrupts" bool "Support for NMI-like interrupts"
depends on BROKEN # 1556553607-46531-1-git-send-email-julien.thierry@arm.com
select CONFIG_ARM_GIC_V3 select CONFIG_ARM_GIC_V3
help help
Adds support for mimicking Non-Maskable Interrupts through the use of Adds support for mimicking Non-Maskable Interrupts through the use of

5
arch/arm64/include/asm/cpucaps.h
View File

@ -53,7 +53,7 @@
#define ARM64_HAS_STAGE2_FWB 32 #define ARM64_HAS_STAGE2_FWB 32
#define ARM64_HAS_CRC32 33 #define ARM64_HAS_CRC32 33
#define ARM64_SSBS 34 #define ARM64_SSBS 34
#define ARM64_WORKAROUND_1188873 35 #define ARM64_WORKAROUND_1418040 35
#define ARM64_HAS_SB 36 #define ARM64_HAS_SB 36
#define ARM64_WORKAROUND_1165522 37 #define ARM64_WORKAROUND_1165522 37
#define ARM64_HAS_ADDRESS_AUTH_ARCH 38 #define ARM64_HAS_ADDRESS_AUTH_ARCH 38
@ -62,7 +62,8 @@
#define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41 #define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41
#define ARM64_HAS_IRQ_PRIO_MASKING 42 #define ARM64_HAS_IRQ_PRIO_MASKING 42
#define ARM64_HAS_DCPODP 43 #define ARM64_HAS_DCPODP 43
#define ARM64_WORKAROUND_1463225 44
#define ARM64_NCAPS 44 #define ARM64_NCAPS 45
#endif /* __ASM_CPUCAPS_H */ #endif /* __ASM_CPUCAPS_H */

18
arch/arm64/include/asm/insn.h
View File

@ -18,6 +18,7 @@
*/ */
#ifndef __ASM_INSN_H #ifndef __ASM_INSN_H
#define __ASM_INSN_H #define __ASM_INSN_H
#include <linux/build_bug.h>
#include <linux/types.h> #include <linux/types.h>
/* A64 instructions are always 32 bits. */ /* A64 instructions are always 32 bits. */
@ -266,18 +267,23 @@ enum aarch64_insn_adr_type {
AARCH64_INSN_ADR_TYPE_ADR, AARCH64_INSN_ADR_TYPE_ADR,
}; };
#define __AARCH64_INSN_FUNCS(abbr, mask, val) \ #define __AARCH64_INSN_FUNCS(abbr, mask, val) \
static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
{ return (code & (mask)) == (val); } \ { \
static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ BUILD_BUG_ON(~(mask) & (val)); \
{ return (val); } return (code & (mask)) == (val); \
} \
static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
{ \
return (val); \
}
__AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000) __AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000)
__AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000) __AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000)
__AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000) __AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000)
__AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000) __AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000)
__AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800) __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
__AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0xB8200000) __AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
__AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800) __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
__AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000)
__AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000) __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)

3
arch/arm64/include/asm/kvm_host.h
View File

@ -592,9 +592,6 @@ static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
void kvm_clr_pmu_events(u32 clr); void kvm_clr_pmu_events(u32 clr);
void __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt);
bool __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt);
void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
#else #else

2
arch/arm64/include/asm/syscall.h
View File

@ -20,7 +20,7 @@
#include <linux/compat.h> #include <linux/compat.h>
#include <linux/err.h> #include <linux/err.h>
typedef long (*syscall_fn_t)(struct pt_regs *regs); typedef long (*syscall_fn_t)(const struct pt_regs *regs);
extern const syscall_fn_t sys_call_table[]; extern const syscall_fn_t sys_call_table[];

18
arch/arm64/include/asm/syscall_wrapper.h
View File

@ -30,10 +30,10 @@
} \ } \
static inline long __do_compat_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__)) static inline long __do_compat_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__))
#define COMPAT_SYSCALL_DEFINE0(sname) \ #define COMPAT_SYSCALL_DEFINE0(sname) \
asmlinkage long __arm64_compat_sys_##sname(void); \ asmlinkage long __arm64_compat_sys_##sname(const struct pt_regs *__unused); \
ALLOW_ERROR_INJECTION(__arm64_compat_sys_##sname, ERRNO); \ ALLOW_ERROR_INJECTION(__arm64_compat_sys_##sname, ERRNO); \
asmlinkage long __arm64_compat_sys_##sname(void) asmlinkage long __arm64_compat_sys_##sname(const struct pt_regs *__unused)
#define COND_SYSCALL_COMPAT(name) \ #define COND_SYSCALL_COMPAT(name) \
cond_syscall(__arm64_compat_sys_##name); cond_syscall(__arm64_compat_sys_##name);
@ -62,11 +62,11 @@
static inline long __do_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__)) static inline long __do_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__))
#ifndef SYSCALL_DEFINE0 #ifndef SYSCALL_DEFINE0
#define SYSCALL_DEFINE0(sname) \ #define SYSCALL_DEFINE0(sname) \
SYSCALL_METADATA(_##sname, 0); \ SYSCALL_METADATA(_##sname, 0); \
asmlinkage long __arm64_sys_##sname(void); \ asmlinkage long __arm64_sys_##sname(const struct pt_regs *__unused); \
ALLOW_ERROR_INJECTION(__arm64_sys_##sname, ERRNO); \ ALLOW_ERROR_INJECTION(__arm64_sys_##sname, ERRNO); \
asmlinkage long __arm64_sys_##sname(void) asmlinkage long __arm64_sys_##sname(const struct pt_regs *__unused)
#endif #endif
#ifndef COND_SYSCALL #ifndef COND_SYSCALL

48
arch/arm64/kernel/cpu_errata.c
View File

@ -502,6 +502,22 @@ static const struct midr_range arm64_ssb_cpus[] = {
{}, {},
}; };
#ifdef CONFIG_ARM64_ERRATUM_1463225
DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
static bool
has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
int scope)
{
u32 midr = read_cpuid_id();
/* Cortex-A76 r0p0 - r3p1 */
struct midr_range range = MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1);
WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
return is_midr_in_range(midr, &range) && is_kernel_in_hyp_mode();
}
#endif
static void __maybe_unused static void __maybe_unused
cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
{ {
@ -682,12 +698,16 @@ static const struct midr_range workaround_clean_cache[] = {
}; };
#endif #endif
#ifdef CONFIG_ARM64_ERRATUM_1188873 #ifdef CONFIG_ARM64_ERRATUM_1418040
static const struct midr_range erratum_1188873_list[] = { /*
/* Cortex-A76 r0p0 to r2p0 */ * - 1188873 affects r0p0 to r2p0
MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), * - 1418040 affects r0p0 to r3p1
/* Neoverse-N1 r0p0 to r2p0 */ */
MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 2, 0), static const struct midr_range erratum_1418040_list[] = {
/* Cortex-A76 r0p0 to r3p1 */
MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
/* Neoverse-N1 r0p0 to r3p1 */
MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
{}, {},
}; };
#endif #endif
@ -809,11 +829,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
.matches = has_ssbd_mitigation, .matches = has_ssbd_mitigation,
.midr_range_list = arm64_ssb_cpus, .midr_range_list = arm64_ssb_cpus,
}, },
#ifdef CONFIG_ARM64_ERRATUM_1188873 #ifdef CONFIG_ARM64_ERRATUM_1418040
{ {
.desc = "ARM erratum 1188873", .desc = "ARM erratum 1418040",
.capability = ARM64_WORKAROUND_1188873, .capability = ARM64_WORKAROUND_1418040,
ERRATA_MIDR_RANGE_LIST(erratum_1188873_list), ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
}, },
#endif #endif
#ifdef CONFIG_ARM64_ERRATUM_1165522 #ifdef CONFIG_ARM64_ERRATUM_1165522
@ -823,6 +843,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
.capability = ARM64_WORKAROUND_1165522, .capability = ARM64_WORKAROUND_1165522,
ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
}, },
#endif
#ifdef CONFIG_ARM64_ERRATUM_1463225
{
.desc = "ARM erratum 1463225",
.capability = ARM64_WORKAROUND_1463225,
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
.matches = has_cortex_a76_erratum_1463225,
},
#endif #endif
{ {
} }

4
arch/arm64/kernel/entry.S
View File

@ -336,8 +336,8 @@ alternative_if ARM64_WORKAROUND_845719
alternative_else_nop_endif alternative_else_nop_endif
#endif #endif
3: 3:
#ifdef CONFIG_ARM64_ERRATUM_1188873 #ifdef CONFIG_ARM64_ERRATUM_1418040
alternative_if_not ARM64_WORKAROUND_1188873 alternative_if_not ARM64_WORKAROUND_1418040
b 4f b 4f
alternative_else_nop_endif alternative_else_nop_endif
/* /*

6
arch/arm64/kernel/kaslr.c
View File

@ -145,15 +145,15 @@ u64 __init kaslr_early_init(u64 dt_phys)
if (IS_ENABLED(CONFIG_RANDOMIZE_MODULE_REGION_FULL)) { if (IS_ENABLED(CONFIG_RANDOMIZE_MODULE_REGION_FULL)) {
/* /*
* Randomize the module region over a 4 GB window covering the * Randomize the module region over a 2 GB window covering the
* kernel. This reduces the risk of modules leaking information * kernel. This reduces the risk of modules leaking information
* about the address of the kernel itself, but results in * about the address of the kernel itself, but results in
* branches between modules and the core kernel that are * branches between modules and the core kernel that are
* resolved via PLTs. (Branches between modules will be * resolved via PLTs. (Branches between modules will be
* resolved normally.) * resolved normally.)
*/ */
module_range = SZ_4G - (u64)(_end - _stext); module_range = SZ_2G - (u64)(_end - _stext);
module_alloc_base = max((u64)_end + offset - SZ_4G, module_alloc_base = max((u64)_end + offset - SZ_2G,
(u64)MODULES_VADDR); (u64)MODULES_VADDR);
} else { } else {
/* /*

44
arch/arm64/kernel/module.c
View File

@ -56,7 +56,7 @@ void *module_alloc(unsigned long size)
* can simply omit this fallback in that case. * can simply omit this fallback in that case.
*/ */
p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base, p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
module_alloc_base + SZ_4G, GFP_KERNEL, module_alloc_base + SZ_2G, GFP_KERNEL,
PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE, PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
__builtin_return_address(0)); __builtin_return_address(0));
@ -96,16 +96,50 @@ static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
{ {
s64 sval = do_reloc(op, place, val); s64 sval = do_reloc(op, place, val);
/*
* The ELF psABI for AArch64 documents the 16-bit and 32-bit place
* relative and absolute relocations as having a range of [-2^15, 2^16)
* or [-2^31, 2^32), respectively. However, in order to be able to
* detect overflows reliably, we have to choose whether we interpret
* such quantities as signed or as unsigned, and stick with it.
* The way we organize our address space requires a signed
* interpretation of 32-bit relative references, so let's use that
* for all R_AARCH64_PRELxx relocations. This means our upper
* bound for overflow detection should be Sxx_MAX rather than Uxx_MAX.
*/
switch (len) { switch (len) {
case 16: case 16:
*(s16 *)place = sval; *(s16 *)place = sval;
if (sval < S16_MIN || sval > U16_MAX) switch (op) {
return -ERANGE; case RELOC_OP_ABS:
if (sval < 0 || sval > U16_MAX)
return -ERANGE;
break;
case RELOC_OP_PREL:
if (sval < S16_MIN || sval > S16_MAX)
return -ERANGE;
break;
default:
pr_err("Invalid 16-bit data relocation (%d)\n", op);
return 0;
}
break; break;
case 32: case 32:
*(s32 *)place = sval; *(s32 *)place = sval;
if (sval < S32_MIN || sval > U32_MAX) switch (op) {
return -ERANGE; case RELOC_OP_ABS:
if (sval < 0 || sval > U32_MAX)
return -ERANGE;
break;
case RELOC_OP_PREL:
if (sval < S32_MIN || sval > S32_MAX)
return -ERANGE;
break;
default:
pr_err("Invalid 32-bit data relocation (%d)\n", op);
return 0;
}
break; break;
case 64: case 64:
*(s64 *)place = sval; *(s64 *)place = sval;

16
arch/arm64/kernel/sys.c
View File

@ -47,22 +47,26 @@ SYSCALL_DEFINE1(arm64_personality, unsigned int, personality)
return ksys_personality(personality); return ksys_personality(personality);
} }
asmlinkage long sys_ni_syscall(void);
asmlinkage long __arm64_sys_ni_syscall(const struct pt_regs *__unused)
{
return sys_ni_syscall();
}
/* /*
* Wrappers to pass the pt_regs argument. * Wrappers to pass the pt_regs argument.
*/ */
#define sys_personality sys_arm64_personality #define __arm64_sys_personality __arm64_sys_arm64_personality
asmlinkage long sys_ni_syscall(const struct pt_regs *);
#define __arm64_sys_ni_syscall sys_ni_syscall
#undef __SYSCALL #undef __SYSCALL
#define __SYSCALL(nr, sym) asmlinkage long __arm64_##sym(const struct pt_regs *); #define __SYSCALL(nr, sym) asmlinkage long __arm64_##sym(const struct pt_regs *);
#include <asm/unistd.h> #include <asm/unistd.h>
#undef __SYSCALL #undef __SYSCALL
#define __SYSCALL(nr, sym) [nr] = (syscall_fn_t)__arm64_##sym, #define __SYSCALL(nr, sym) [nr] = __arm64_##sym,
const syscall_fn_t sys_call_table[__NR_syscalls] = { const syscall_fn_t sys_call_table[__NR_syscalls] = {
[0 ... __NR_syscalls - 1] = (syscall_fn_t)sys_ni_syscall, [0 ... __NR_syscalls - 1] = __arm64_sys_ni_syscall,
#include <asm/unistd.h> #include <asm/unistd.h>
}; };

7
arch/arm64/kernel/sys32.c
View File

@ -133,17 +133,14 @@ COMPAT_SYSCALL_DEFINE6(aarch32_fallocate, int, fd, int, mode,
return ksys_fallocate(fd, mode, arg_u64(offset), arg_u64(len)); return ksys_fallocate(fd, mode, arg_u64(offset), arg_u64(len));
} }
asmlinkage long sys_ni_syscall(const struct pt_regs *);
#define __arm64_sys_ni_syscall sys_ni_syscall
#undef __SYSCALL #undef __SYSCALL
#define __SYSCALL(nr, sym) asmlinkage long __arm64_##sym(const struct pt_regs *); #define __SYSCALL(nr, sym) asmlinkage long __arm64_##sym(const struct pt_regs *);
#include <asm/unistd32.h> #include <asm/unistd32.h>
#undef __SYSCALL #undef __SYSCALL
#define __SYSCALL(nr, sym) [nr] = (syscall_fn_t)__arm64_##sym, #define __SYSCALL(nr, sym) [nr] = __arm64_##sym,
const syscall_fn_t compat_sys_call_table[__NR_compat_syscalls] = { const syscall_fn_t compat_sys_call_table[__NR_compat_syscalls] = {
[0 ... __NR_compat_syscalls - 1] = (syscall_fn_t)sys_ni_syscall, [0 ... __NR_compat_syscalls - 1] = __arm64_sys_ni_syscall,
#include <asm/unistd32.h> #include <asm/unistd32.h>
}; };

31
arch/arm64/kernel/syscall.c
View File

@ -8,6 +8,7 @@
#include <linux/syscalls.h> #include <linux/syscalls.h>
#include <asm/daifflags.h> #include <asm/daifflags.h>
#include <asm/debug-monitors.h>
#include <asm/fpsimd.h> #include <asm/fpsimd.h>
#include <asm/syscall.h> #include <asm/syscall.h>
#include <asm/thread_info.h> #include <asm/thread_info.h>
@ -60,6 +61,35 @@ static inline bool has_syscall_work(unsigned long flags)
int syscall_trace_enter(struct pt_regs *regs); int syscall_trace_enter(struct pt_regs *regs);
void syscall_trace_exit(struct pt_regs *regs); void syscall_trace_exit(struct pt_regs *regs);
#ifdef CONFIG_ARM64_ERRATUM_1463225
DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
static void cortex_a76_erratum_1463225_svc_handler(void)
{
u32 reg, val;
if (!unlikely(test_thread_flag(TIF_SINGLESTEP)))
return;
if (!unlikely(this_cpu_has_cap(ARM64_WORKAROUND_1463225)))
return;
__this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 1);
reg = read_sysreg(mdscr_el1);
val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE;
write_sysreg(val, mdscr_el1);
asm volatile("msr daifclr, #8");
isb();
/* We will have taken a single-step exception by this point */
write_sysreg(reg, mdscr_el1);
__this_cpu_write(__in_cortex_a76_erratum_1463225_wa, 0);
}
#else
static void cortex_a76_erratum_1463225_svc_handler(void) { }
#endif /* CONFIG_ARM64_ERRATUM_1463225 */
static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr,
const syscall_fn_t syscall_table[]) const syscall_fn_t syscall_table[])
{ {
@ -68,6 +98,7 @@ static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr,
regs->orig_x0 = regs->regs[0]; regs->orig_x0 = regs->regs[0];
regs->syscallno = scno; regs->syscallno = scno;
cortex_a76_erratum_1463225_svc_handler();
local_daif_restore(DAIF_PROCCTX); local_daif_restore(DAIF_PROCCTX);
user_exit(); user_exit();

9
arch/arm64/kernel/traps.c
View File

@ -168,7 +168,6 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
static int __die(const char *str, int err, struct pt_regs *regs) static int __die(const char *str, int err, struct pt_regs *regs)
{ {
struct task_struct *tsk = current;
static int die_counter; static int die_counter;
int ret; int ret;
@ -181,9 +180,6 @@ static int __die(const char *str, int err, struct pt_regs *regs)
return ret; return ret;
print_modules(); print_modules();
pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n",
TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk),
end_of_stack(tsk));
show_regs(regs); show_regs(regs);
if (!user_mode(regs)) if (!user_mode(regs))
@ -256,7 +252,10 @@ void arm64_force_sig_fault(int signo, int code, void __user *addr,
const char *str) const char *str)
{ {
arm64_show_signal(signo, str); arm64_show_signal(signo, str);
force_sig_fault(signo, code, addr, current); if (signo == SIGKILL)
force_sig(SIGKILL, current);
else
force_sig_fault(signo, code, addr, current);
} }
void arm64_force_sig_mceerr(int code, void __user *addr, short lsb, void arm64_force_sig_mceerr(int code, void __user *addr, short lsb,

1
arch/arm64/kvm/hyp/Makefile
View File

@ -10,6 +10,7 @@ KVM=../../../../virt/kvm
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/aarch32.o
obj-$(CONFIG_KVM_ARM_HOST) += vgic-v2-cpuif-proxy.o obj-$(CONFIG_KVM_ARM_HOST) += vgic-v2-cpuif-proxy.o
obj-$(CONFIG_KVM_ARM_HOST) += sysreg-sr.o obj-$(CONFIG_KVM_ARM_HOST) += sysreg-sr.o

39
arch/arm64/kvm/hyp/switch.c
View File

@ -16,6 +16,7 @@
*/ */
#include <linux/arm-smccc.h> #include <linux/arm-smccc.h>
#include <linux/kvm_host.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/jump_label.h> #include <linux/jump_label.h>
#include <uapi/linux/psci.h> #include <uapi/linux/psci.h>
@ -505,6 +506,44 @@ static void __hyp_text __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
#endif #endif
} }
/**
* Disable host events, enable guest events
*/
static bool __hyp_text __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt)
{
struct kvm_host_data *host;
struct kvm_pmu_events *pmu;
host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
pmu = &host->pmu_events;
if (pmu->events_host)
write_sysreg(pmu->events_host, pmcntenclr_el0);
if (pmu->events_guest)
write_sysreg(pmu->events_guest, pmcntenset_el0);
return (pmu->events_host || pmu->events_guest);
}
/**
* Disable guest events, enable host events
*/
static void __hyp_text __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt)
{
struct kvm_host_data *host;
struct kvm_pmu_events *pmu;
host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
pmu = &host->pmu_events;
if (pmu->events_guest)
write_sysreg(pmu->events_guest, pmcntenclr_el0);
if (pmu->events_host)
write_sysreg(pmu->events_host, pmcntenset_el0);
}
/* Switch to the guest for VHE systems running in EL2 */ /* Switch to the guest for VHE systems running in EL2 */
int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
{ {

38
arch/arm64/kvm/pmu.c
View File

@ -53,44 +53,6 @@ void kvm_clr_pmu_events(u32 clr)
ctx->pmu_events.events_guest &= ~clr; ctx->pmu_events.events_guest &= ~clr;
} }
/**
* Disable host events, enable guest events
*/
bool __hyp_text __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt)
{
struct kvm_host_data *host;
struct kvm_pmu_events *pmu;
host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
pmu = &host->pmu_events;
if (pmu->events_host)
write_sysreg(pmu->events_host, pmcntenclr_el0);
if (pmu->events_guest)
write_sysreg(pmu->events_guest, pmcntenset_el0);
return (pmu->events_host || pmu->events_guest);
}
/**
* Disable guest events, enable host events
*/
void __hyp_text __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt)
{
struct kvm_host_data *host;
struct kvm_pmu_events *pmu;
host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
pmu = &host->pmu_events;
if (pmu->events_guest)
write_sysreg(pmu->events_guest, pmcntenclr_el0);
if (pmu->events_host)
write_sysreg(pmu->events_host, pmcntenset_el0);
}
#define PMEVTYPER_READ_CASE(idx) \ #define PMEVTYPER_READ_CASE(idx) \
case idx: \ case idx: \
return read_sysreg(pmevtyper##idx##_el0) return read_sysreg(pmevtyper##idx##_el0)

33
arch/arm64/mm/fault.c
View File

@ -811,6 +811,36 @@ void __init hook_debug_fault_code(int nr,
debug_fault_info[nr].name = name; debug_fault_info[nr].name = name;
} }
#ifdef CONFIG_ARM64_ERRATUM_1463225
DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
static int __exception
cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
{
if (user_mode(regs))
return 0;
if (!__this_cpu_read(__in_cortex_a76_erratum_1463225_wa))
return 0;
/*
* We've taken a dummy step exception from the kernel to ensure
* that interrupts are re-enabled on the syscall path. Return back
* to cortex_a76_erratum_1463225_svc_handler() with debug exceptions
* masked so that we can safely restore the mdscr and get on with
* handling the syscall.
*/
regs->pstate |= PSR_D_BIT;
return 1;
}
#else
static int __exception
cortex_a76_erratum_1463225_debug_handler(struct pt_regs *regs)
{
return 0;
}
#endif /* CONFIG_ARM64_ERRATUM_1463225 */
asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint,
unsigned int esr, unsigned int esr,
struct pt_regs *regs) struct pt_regs *regs)
@ -818,6 +848,9 @@ asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint,
const struct fault_info *inf = esr_to_debug_fault_info(esr); const struct fault_info *inf = esr_to_debug_fault_info(esr);
unsigned long pc = instruction_pointer(regs); unsigned long pc = instruction_pointer(regs);
if (cortex_a76_erratum_1463225_debug_handler(regs))
return;
/* /*
* Tell lockdep we disabled irqs in entry.S. Do nothing if they were * Tell lockdep we disabled irqs in entry.S. Do nothing if they were
* already disabled to preserve the last enabled/disabled addresses. * already disabled to preserve the last enabled/disabled addresses.

6
arch/c6x/include/asm/irqflags.h
View File

@ -1,13 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
* C6X IRQ flag handling * C6X IRQ flag handling
* *
* Copyright (C) 2010 Texas Instruments Incorporated * Copyright (C) 2010 Texas Instruments Incorporated
* Written by Mark Salter (msalter@redhat.com) * Written by Mark Salter (msalter@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/ */
#ifndef _ASM_IRQFLAGS_H #ifndef _ASM_IRQFLAGS_H

10
arch/ia64/include/asm/xor.h
View File

@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
* Optimized RAID-5 checksumming functions for IA-64. * Optimized RAID-5 checksumming functions for IA-64.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* You should have received a copy of the GNU General Public License
* (for example /usr/src/linux/COPYING); if not, write to the Free
* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */

10
arch/ia64/lib/xor.S
View File

@ -1,16 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
* arch/ia64/lib/xor.S * arch/ia64/lib/xor.S
* *
* Optimized RAID-5 checksumming functions for IA-64. * Optimized RAID-5 checksumming functions for IA-64.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* You should have received a copy of the GNU General Public License
* (for example /usr/src/linux/COPYING); if not, write to the Free
* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#include <asm/asmmacro.h> #include <asm/asmmacro.h>

1
arch/ia64/mm/numa.c
View File

@ -55,6 +55,7 @@ paddr_to_nid(unsigned long paddr)
return (i < num_node_memblks) ? node_memblk[i].nid : (num_node_memblks ? -1 : 0); return (i < num_node_memblks) ? node_memblk[i].nid : (num_node_memblks ? -1 : 0);
} }
EXPORT_SYMBOL(paddr_to_nid);
#if defined(CONFIG_SPARSEMEM) && defined(CONFIG_NUMA) #if defined(CONFIG_SPARSEMEM) && defined(CONFIG_NUMA)
/* /*

4
arch/m68k/math-emu/fp_arith.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
fp_arith.c: floating-point math routines for the Linux-m68k fp_arith.c: floating-point math routines for the Linux-m68k
@ -8,9 +9,6 @@
Somewhat based on the AlphaLinux floating point emulator, by David Somewhat based on the AlphaLinux floating point emulator, by David
Mosberger-Tang. Mosberger-Tang.
You may copy, modify, and redistribute this file under the terms of
the GNU General Public License, version 2, or any later version, at
your convenience.
*/ */
#include "fp_emu.h" #include "fp_emu.h"

4
arch/m68k/math-emu/fp_arith.h
View File

@ -1,3 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* /*
fp_arith.h: floating-point math routines for the Linux-m68k fp_arith.h: floating-point math routines for the Linux-m68k
@ -8,9 +9,6 @@
Somewhat based on the AlphaLinux floating point emulator, by David Somewhat based on the AlphaLinux floating point emulator, by David
Mosberger-Tang. Mosberger-Tang.
You may copy, modify, and redistribute this file under the terms of
the GNU General Public License, version 2, or any later version, at
your convenience.
*/ */

5
arch/m68k/math-emu/multi_arith.h
View File

@ -1,3 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* multi_arith.h: multi-precision integer arithmetic functions, needed /* multi_arith.h: multi-precision integer arithmetic functions, needed
to do extended-precision floating point. to do extended-precision floating point.
@ -6,9 +7,7 @@
Somewhat based on arch/alpha/math-emu/ieee-math.c, which is (c) Somewhat based on arch/alpha/math-emu/ieee-math.c, which is (c)
David Mosberger-Tang. David Mosberger-Tang.
You may copy, modify, and redistribute this file under the terms of */
the GNU General Public License, version 2, or any later version, at
your convenience. */
/* Note: /* Note:

15
arch/mips/alchemy/board-gpr.c
View File

@ -1,21 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* GPR board platform device registration (Au1550) * GPR board platform device registration (Au1550)
* *
* Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de> * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/delay.h> #include <linux/delay.h>

15
arch/mips/alchemy/board-mtx1.c
View File

@ -1,21 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* MTX-1 platform devices registration (Au1500) * MTX-1 platform devices registration (Au1500)
* *
* Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org> * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/init.h> #include <linux/init.h>

15
arch/mips/alchemy/board-xxs1500.c
View File

@ -1,23 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* BRIEF MODULE DESCRIPTION * BRIEF MODULE DESCRIPTION
* MyCable XXS1500 board support * MyCable XXS1500 board support
* *
* Copyright 2003, 2008 MontaVista Software Inc. * Copyright 2003, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com> * Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>

15
arch/mips/alchemy/devboards/db1000.c
View File

@ -1,22 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* DBAu1000/1500/1100 PBAu1100/1500 board support * DBAu1000/1500/1100 PBAu1100/1500 board support
* *
* Copyright 2000, 2008 MontaVista Software Inc. * Copyright 2000, 2008 MontaVista Software Inc.
* Author: MontaVista Software, Inc. <source@mvista.com> * Author: MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/clk.h> #include <linux/clk.h>

15
arch/mips/alchemy/devboards/db1200.c
View File

@ -1,21 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* DBAu1200/PBAu1200 board platform device registration * DBAu1200/PBAu1200 board platform device registration
* *
* Copyright (C) 2008-2011 Manuel Lauss * Copyright (C) 2008-2011 Manuel Lauss
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/clk.h> #include <linux/clk.h>

15
arch/mips/ar7/clock.c
View File

@ -1,21 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>

15
arch/mips/ar7/gpio.c
View File

@ -1,21 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
* Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org> * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/init.h> #include <linux/init.h>

15
arch/mips/ar7/irq.c
View File

@ -1,20 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org> * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org> * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/interrupt.h> #include <linux/interrupt.h>

15
arch/mips/ar7/memory.c
View File

@ -1,20 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* /*
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <linux/memblock.h> #include <linux/memblock.h>
#include <linux/init.h> #include <linux/init.h>

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