soc: sunxi: Deal with the MBUS DMA offsets in a central place
So far most of the drivers with the MBUS quirks had to duplicate the code to deal with DT compatibility and enforcing the DMA offsets. Let's move for a more maintainable solution by putting everything in a notifier that would take care of setting up the DMA offsets for all the MBUS devices. Suggested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Maxime Ripard
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@ -2,6 +2,14 @@
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#
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# Allwinner sunXi SoC drivers
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#
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config SUNXI_MBUS
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bool
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default ARCH_SUNXI
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help
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Say y to enable the fixups needed to support the Allwinner
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MBUS DMA quirks.
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config SUNXI_SRAM
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bool
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default ARCH_SUNXI
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@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_SUNXI_MBUS) += sunxi_mbus.o
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obj-$(CONFIG_SUNXI_SRAM) += sunxi_sram.o
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132
drivers/soc/sunxi/sunxi_mbus.c
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132
drivers/soc/sunxi/sunxi_mbus.c
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@ -0,0 +1,132 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2020 Maxime Ripard <maxime@cerno.tech> */
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/notifier.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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static const char * const sunxi_mbus_devices[] = {
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/*
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* The display engine virtual devices are not strictly speaking
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* connected to the MBUS, but since DRM will perform all the
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* memory allocations and DMA operations through that device, we
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* need to have the quirk on those devices too.
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*/
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"allwinner,sun4i-a10-display-engine",
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"allwinner,sun5i-a10s-display-engine",
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"allwinner,sun5i-a13-display-engine",
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"allwinner,sun6i-a31-display-engine",
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"allwinner,sun6i-a31s-display-engine",
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"allwinner,sun7i-a20-display-engine",
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"allwinner,sun8i-a23-display-engine",
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"allwinner,sun8i-a33-display-engine",
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"allwinner,sun8i-a83t-display-engine",
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"allwinner,sun8i-h3-display-engine",
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"allwinner,sun8i-r40-display-engine",
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"allwinner,sun8i-v3s-display-engine",
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"allwinner,sun9i-a80-display-engine",
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"allwinner,sun50i-a64-display-engine",
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/*
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* And now we have the regular devices connected to the MBUS
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* (that we know of).
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*/
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"allwinner,sun4i-a10-csi1",
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"allwinner,sun4i-a10-display-backend",
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"allwinner,sun4i-a10-display-frontend",
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"allwinner,sun4i-a10-video-engine",
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"allwinner,sun5i-a13-display-backend",
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"allwinner,sun5i-a13-video-engine",
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"allwinner,sun6i-a31-csi",
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"allwinner,sun6i-a31-display-backend",
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"allwinner,sun7i-a20-csi0",
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"allwinner,sun7i-a20-display-backend",
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"allwinner,sun7i-a20-display-frontend",
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"allwinner,sun7i-a20-video-engine",
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"allwinner,sun8i-a23-display-backend",
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"allwinner,sun8i-a23-display-frontend",
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"allwinner,sun8i-a33-display-backend",
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"allwinner,sun8i-a33-display-frontend",
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"allwinner,sun8i-a33-video-engine",
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"allwinner,sun8i-a83t-csi",
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"allwinner,sun8i-h3-csi",
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"allwinner,sun8i-h3-video-engine",
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"allwinner,sun8i-v3s-csi",
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"allwinner,sun9i-a80-display-backend",
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"allwinner,sun50i-a64-csi",
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"allwinner,sun50i-a64-video-engine",
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"allwinner,sun50i-h5-video-engine",
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NULL,
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};
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static int sunxi_mbus_notifier(struct notifier_block *nb,
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unsigned long event, void *__dev)
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{
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struct device *dev = __dev;
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int ret;
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if (event != BUS_NOTIFY_ADD_DEVICE)
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return NOTIFY_DONE;
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/*
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* Only the devices that need a large memory bandwidth do DMA
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* directly over the memory bus (called MBUS), instead of going
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* through the regular system bus.
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*/
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if (!of_device_compatible_match(dev->of_node, sunxi_mbus_devices))
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return NOTIFY_DONE;
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/*
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* Devices with an interconnects property have the MBUS
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* relationship described in their DT and dealt with by
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* of_dma_configure, so we can just skip them.
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*
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* Older DTs or SoCs who are not clearly understood need to set
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* that DMA offset though.
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*/
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if (of_find_property(dev->of_node, "interconnects", NULL))
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return NOTIFY_DONE;
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ret = dma_direct_set_offset(dev, PHYS_OFFSET, 0, SZ_4G);
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if (ret)
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dev_err(dev, "Couldn't setup our DMA offset: %d\n", ret);
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return NOTIFY_DONE;
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}
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static struct notifier_block sunxi_mbus_nb = {
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.notifier_call = sunxi_mbus_notifier,
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};
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static const char * const sunxi_mbus_platforms[] __initconst = {
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"allwinner,sun4i-a10",
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"allwinner,sun5i-a10s",
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"allwinner,sun5i-a13",
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"allwinner,sun6i-a31",
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"allwinner,sun7i-a20",
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"allwinner,sun8i-a23",
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"allwinner,sun8i-a33",
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"allwinner,sun8i-a83t",
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"allwinner,sun8i-h3",
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"allwinner,sun8i-r40",
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"allwinner,sun8i-v3",
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"allwinner,sun8i-v3s",
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"allwinner,sun9i-a80",
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"allwinner,sun50i-a64",
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"allwinner,sun50i-h5",
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"nextthing,gr8",
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NULL,
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};
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static int __init sunxi_mbus_init(void)
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{
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if (!of_device_compatible_match(of_root, sunxi_mbus_platforms))
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return 0;
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bus_register_notifier(&platform_bus_type, &sunxi_mbus_nb);
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return 0;
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}
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arch_initcall(sunxi_mbus_init);
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