From b4d56e0c508b2ad847aeff5691f67bd2a40034ec Mon Sep 17 00:00:00 2001 From: Wesley Chalmers Date: Thu, 6 May 2021 14:51:20 -0400 Subject: [PATCH] drm/amd/display: Add Interface to set FIFO ERRDET SW Override [WHY] HW has handed down a new sequence which requires access to the FIFO ERRDET SW Override register. Signed-off-by: Wesley Chalmers Reviewed-by: Dmytro Laktyushkin Acked-by: Stylon Wang Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 10 +++++++ .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 29 +++++++++++++++++-- .../gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c | 1 + .../gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c | 1 + .../drm/amd/display/dc/dcn301/dcn301_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 2 ++ 6 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c index 8774406120fc..5679983158e2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c @@ -96,6 +96,15 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg, return; } +void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, + bool en) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, + DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0); +} + void dccg2_init(struct dccg *dccg) { } @@ -103,6 +112,7 @@ void dccg2_init(struct dccg *dccg) static const struct dccg_funcs dccg2_funcs = { .update_dpp_dto = dccg2_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .dccg_init = dccg2_init }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h index e5aa2da3176d..5203ee0a65aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h @@ -34,7 +34,8 @@ DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ - SR(REFCLK_CNTL) + SR(REFCLK_CNTL),\ + SR(DISPCLK_FREQ_CHANGE_CNTL) #define DCCG_REG_LIST_DCN2() \ DCCG_COMMON_REG_LIST_DCN_BASE(),\ @@ -59,7 +60,16 @@ DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ - DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh) + DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh) + #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \ DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ @@ -74,7 +84,16 @@ type DPPCLK_DTO_ENABLE[6];\ type DPPCLK_DTO_DB_EN[6];\ type REFCLK_CLOCK_EN;\ - type REFCLK_SRC_SEL; + type REFCLK_SRC_SEL;\ + type DISPCLK_STEP_DELAY;\ + type DISPCLK_STEP_SIZE;\ + type DISPCLK_FREQ_RAMP_DONE;\ + type DISPCLK_MAX_ERRDET_CYCLES;\ + type DCCG_FIFO_ERRDET_RESET;\ + type DCCG_FIFO_ERRDET_STATE;\ + type DCCG_FIFO_ERRDET_OVR_EN;\ + type DISPCLK_CHG_FWD_CORR_DISABLE;\ + type DISPCLK_FREQ_CHANGE_CNTL; #define DCCG3_REG_FIELD_LIST(type) \ type PHYASYMCLK_FORCE_EN;\ @@ -137,6 +156,7 @@ struct dccg_registers { uint32_t DPPCLK_DTO_CTRL; uint32_t DPPCLK_DTO_PARAM[6]; uint32_t REFCLK_CNTL; + uint32_t DISPCLK_FREQ_CHANGE_CNTL; uint32_t HDMICHARCLK_CLOCK_CNTL[6]; uint32_t PHYASYMCLK_CLOCK_CNTL; uint32_t PHYBSYMCLK_CLOCK_CNTL; @@ -171,6 +191,9 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz); +void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, + bool en); + void dccg2_init(struct dccg *dccg); struct dccg *dccg2_create( diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c index 60cf3ff68cb0..6e1befbb4458 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c @@ -100,6 +100,7 @@ void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) static const struct dccg_funcs dccg21_funcs = { .update_dpp_dto = dccg21_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .dccg_init = dccg2_init }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c index b822a13e40ce..570f6eacd4e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c @@ -46,6 +46,7 @@ static const struct dccg_funcs dccg3_funcs = { .update_dpp_dto = dccg2_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .dccg_init = dccg2_init }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c index 420da414929c..6e6af02b38f9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c @@ -45,6 +45,7 @@ static const struct dccg_funcs dccg301_funcs = { .update_dpp_dto = dccg2_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .dccg_init = dccg2_init }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index f7aa703e3175..d3d7c338e491 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -76,6 +76,8 @@ struct dccg_funcs { void (*get_dccg_ref_freq)(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz); + void (*set_fifo_errdet_ovr_en)(struct dccg *dccg, + bool en); void (*dccg_init)(struct dccg *dccg); #if defined(CONFIG_DRM_AMD_DC_DCN3_1)