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pinctrl/amd: Remove the default de-bounce time

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commit 8cf4345575a416e6856a6856ac6eaa31ad883126 upstream.

In the function amd_gpio_irq_enable() and
amd_gpio_direction_input(), remove the code which is setting
the default de-bounce time to 2.75ms.

The driver code shall use the same settings as specified in
BIOS. Any default assignment impacts TouchPad behaviour when
the LevelTrig is set to EDGE FALLING.

Reviewed-by:  Ken Xue <Ken.Xue@amd.com>
Signed-off-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Agrawal, Nitesh-kumar 2016-07-26 08:28:19 +00:00 committed by Greg Kroah-Hartman
parent d860213f8b
commit b518b0c853
1 changed files with 0 additions and 20 deletions
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20
drivers/pinctrl/pinctrl-amd.c
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@ -48,17 +48,6 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + offset * 4);
/*
* Suppose BIOS or Bootloader sets specific debounce for the
* GPIO. if not, set debounce to be 2.75ms and remove glitch.
*/
if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
pin_reg |= 0xf;
pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
}
pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
writel(pin_reg, gpio_dev->base + offset * 4);
spin_unlock_irqrestore(&gpio_dev->lock, flags);
@ -331,15 +320,6 @@ static void amd_gpio_irq_enable(struct irq_data *d)
spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
/*
Suppose BIOS or Bootloader sets specific debounce for the
GPIO. if not, set debounce to be 2.75ms.
*/
if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
pin_reg |= 0xf;
pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
}
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);