powerpc: Improve FSCR init and context switching
This fixes a few issues with FSCR init and switching. In commit 152d523e6307 ("powerpc: Create context switch helpers save_sprs() and restore_sprs()") we moved the setting of the FSCR register from inside an CPU_FTR_ARCH_207S section to inside just a CPU_FTR_ARCH_DSCR section. Hence we are setting FSCR on POWER6/7 where the FSCR doesn't exist. This is harmless but we shouldn't do it. Also, we can simplify the FSCR context switch. We don't need to go through the calculation involving dscr_inherit. We can just restore what we saved last time. We also set an initial value in INIT_THREAD, so that pid 1 which is cloned from that gets a sane value. Based on patch by Jack Miller. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -347,6 +347,7 @@ struct thread_struct {
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.fs = KERNEL_DS, \
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.fpexc_mode = 0, \
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.ppr = INIT_PPR, \
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.fscr = FSCR_TAR | FSCR_EBB \
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}
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#endif
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@ -1031,18 +1031,11 @@ static inline void restore_sprs(struct thread_struct *old_thread,
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#ifdef CONFIG_PPC_BOOK3S_64
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if (cpu_has_feature(CPU_FTR_DSCR)) {
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u64 dscr = get_paca()->dscr_default;
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u64 fscr = old_thread->fscr & ~FSCR_DSCR;
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if (new_thread->dscr_inherit) {
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if (new_thread->dscr_inherit)
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dscr = new_thread->dscr;
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fscr |= FSCR_DSCR;
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}
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if (old_thread->dscr != dscr)
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mtspr(SPRN_DSCR, dscr);
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if (old_thread->fscr != fscr)
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mtspr(SPRN_FSCR, fscr);
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}
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if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
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@ -1053,6 +1046,9 @@ static inline void restore_sprs(struct thread_struct *old_thread,
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if (old_thread->ebbrr != new_thread->ebbrr)
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mtspr(SPRN_EBBRR, new_thread->ebbrr);
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if (old_thread->fscr != new_thread->fscr)
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mtspr(SPRN_FSCR, new_thread->fscr);
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if (old_thread->tar != new_thread->tar)
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mtspr(SPRN_TAR, new_thread->tar);
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}
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@ -1419,7 +1419,8 @@ void facility_unavailable_exception(struct pt_regs *regs)
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rd = (instword >> 21) & 0x1f;
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current->thread.dscr = regs->gpr[rd];
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current->thread.dscr_inherit = 1;
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mtspr(SPRN_FSCR, value | FSCR_DSCR);
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current->thread.fscr |= FSCR_DSCR;
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mtspr(SPRN_FSCR, current->thread.fscr);
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}
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/* Read from DSCR (mfspr RT, 0x03) */
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