drm/nouveau/fault/tu102: switch to explicit intr handlers
- reads vectors from HW, rather than being hardcoded - removes hacks to support routing via old interfaces Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs
parent
e650738055
commit
b59d810a47
@ -7,6 +7,8 @@ struct nvkm_fault {
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const struct nvkm_fault_func *func;
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struct nvkm_subdev subdev;
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struct nvkm_inth info_fault;
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struct nvkm_fault_buffer *buffer[2];
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int buffer_nr;
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@ -16,6 +16,8 @@ struct nvkm_fault_buffer {
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u32 put;
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struct nvkm_memory *mem;
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u64 addr;
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struct nvkm_inth inth;
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};
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int nvkm_fault_new_(const struct nvkm_fault_func *, struct nvkm_device *, enum nvkm_subdev_type,
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@ -24,20 +24,27 @@
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#include <core/memory.h>
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#include <subdev/mc.h>
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#include <subdev/mmu.h>
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#include <subdev/vfn.h>
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#include <engine/fifo.h>
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#include <nvif/class.h>
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static irqreturn_t
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tu102_fault_buffer_notify(struct nvkm_inth *inth)
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{
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struct nvkm_fault_buffer *buffer = container_of(inth, typeof(*buffer), inth);
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nvkm_event_ntfy(&buffer->fault->event, buffer->id, NVKM_FAULT_BUFFER_EVENT_PENDING);
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return IRQ_HANDLED;
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}
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static void
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tu102_fault_buffer_intr(struct nvkm_fault_buffer *buffer, bool enable)
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{
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/*XXX: Earlier versions of RM touched the old regs on Turing,
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* which don't appear to actually work anymore, but newer
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* versions of RM don't appear to touch anything at all..
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*/
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struct nvkm_device *device = buffer->fault->subdev.device;
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nvkm_mc_intr_mask(device, NVKM_SUBDEV_FAULT, 0, enable);
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if (enable)
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nvkm_inth_allow(&buffer->inth);
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else
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nvkm_inth_block(&buffer->inth);
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}
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static void
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@ -46,10 +53,6 @@ tu102_fault_buffer_fini(struct nvkm_fault_buffer *buffer)
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struct nvkm_device *device = buffer->fault->subdev.device;
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const u32 foff = buffer->id * 0x20;
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/* Disable the fault interrupts */
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nvkm_wr32(device, 0xb81408, 0x1);
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nvkm_wr32(device, 0xb81410, 0x10);
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nvkm_mask(device, 0xb83010 + foff, 0x80000000, 0x00000000);
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}
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@ -59,10 +62,6 @@ tu102_fault_buffer_init(struct nvkm_fault_buffer *buffer)
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struct nvkm_device *device = buffer->fault->subdev.device;
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const u32 foff = buffer->id * 0x20;
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/* Enable the fault interrupts */
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nvkm_wr32(device, 0xb81208, 0x1);
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nvkm_wr32(device, 0xb81210, 0x10);
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nvkm_mask(device, 0xb83010 + foff, 0xc0000000, 0x40000000);
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nvkm_wr32(device, 0xb83004 + foff, upper_32_bits(buffer->addr));
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nvkm_wr32(device, 0xb83000 + foff, lower_32_bits(buffer->addr));
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@ -82,9 +81,10 @@ tu102_fault_buffer_info(struct nvkm_fault_buffer *buffer)
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buffer->put = 0xb8300c + foff;
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}
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static void
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tu102_fault_intr_fault(struct nvkm_fault *fault)
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static irqreturn_t
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tu102_fault_info_fault(struct nvkm_inth *inth)
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{
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struct nvkm_fault *fault = container_of(inth, typeof(*fault), info_fault);
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struct nvkm_subdev *subdev = &fault->subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_fault_data info;
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@ -106,45 +106,9 @@ tu102_fault_intr_fault(struct nvkm_fault *fault)
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info.reason = (info1 & 0x0000001f);
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nvkm_fifo_fault(device->fifo, &info);
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}
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static void
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tu102_fault_intr(struct nvkm_fault *fault)
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{
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struct nvkm_subdev *subdev = &fault->subdev;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0xb83094);
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if (stat & 0x80000000) {
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tu102_fault_intr_fault(fault);
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nvkm_wr32(device, 0xb83094, 0x80000000);
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stat &= ~0x80000000;
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}
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if (stat & 0x00000200) {
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/* Clear the associated interrupt flag */
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nvkm_wr32(device, 0xb81010, 0x10);
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if (fault->buffer[0]) {
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nvkm_event_ntfy(&fault->event, 0, NVKM_FAULT_BUFFER_EVENT_PENDING);
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stat &= ~0x00000200;
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}
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}
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/* Replayable MMU fault */
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if (stat & 0x00000100) {
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/* Clear the associated interrupt flag */
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nvkm_wr32(device, 0xb81008, 0x1);
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if (fault->buffer[1]) {
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nvkm_event_ntfy(&fault->event, 1, NVKM_FAULT_BUFFER_EVENT_PENDING);
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stat &= ~0x00000100;
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}
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}
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if (stat) {
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nvkm_debug(subdev, "intr %08x\n", stat);
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}
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nvkm_wr32(device, 0xb83094, 0x80000000);
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return IRQ_HANDLED;
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}
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static void
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@ -155,23 +119,48 @@ tu102_fault_fini(struct nvkm_fault *fault)
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if (fault->buffer[0])
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fault->func->buffer.fini(fault->buffer[0]);
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/*XXX: disable priv faults */
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nvkm_inth_block(&fault->info_fault);
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}
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static void
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tu102_fault_init(struct nvkm_fault *fault)
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{
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/*XXX: enable priv faults */
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nvkm_inth_allow(&fault->info_fault);
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fault->func->buffer.init(fault->buffer[0]);
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nvkm_event_ntfy_allow(&fault->nrpfb);
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}
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static int
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tu102_fault_oneinit(struct nvkm_fault *fault)
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{
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struct nvkm_device *device = fault->subdev.device;
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struct nvkm_intr *intr = &device->vfn->intr;
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int ret, i;
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ret = nvkm_inth_add(intr, nvkm_rd32(device, 0x100ee0) & 0x0000ffff,
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NVKM_INTR_PRIO_NORMAL, &fault->subdev, tu102_fault_info_fault,
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&fault->info_fault);
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if (ret)
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return ret;
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for (i = 0; i < fault->buffer_nr; i++) {
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ret = nvkm_inth_add(intr, nvkm_rd32(device, 0x100ee4 + (i * 4)) >> 16,
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NVKM_INTR_PRIO_NORMAL, &fault->subdev,
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tu102_fault_buffer_notify, &fault->buffer[i]->inth);
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if (ret)
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return ret;
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}
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return gv100_fault_oneinit(fault);
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}
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static const struct nvkm_fault_func
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tu102_fault = {
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.oneinit = gv100_fault_oneinit,
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.oneinit = tu102_fault_oneinit,
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.init = tu102_fault_init,
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.fini = tu102_fault_fini,
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.intr = tu102_fault_intr,
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.buffer.nr = 2,
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.buffer.entry_size = 32,
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.buffer.info = tu102_fault_buffer_info,
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@ -39,11 +39,6 @@ tu102_mc_intr_update(struct tu102_mc *mc)
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nvkm_wr32(device, 0x000180 + (i * 0x04), ~mask);
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nvkm_wr32(device, 0x000160 + (i * 0x04), mask);
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}
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if (mask & 0x00000200)
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nvkm_wr32(device, 0xb81608, 0x6);
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else
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nvkm_wr32(device, 0xb81610, 0x6);
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}
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static void
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@ -88,14 +83,6 @@ tu102_mc_intr_stat(struct nvkm_mc *mc)
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struct nvkm_device *device = mc->subdev.device;
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u32 intr0 = nvkm_rd32(device, 0x000100);
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u32 intr1 = nvkm_rd32(device, 0x000104);
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u32 intr_top = nvkm_rd32(device, 0xb81600);
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/* Turing and above route the MMU fault interrupts via a different
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* interrupt tree with different control registers. For the moment remap
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* them back to the old PMC vector.
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*/
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if (intr_top & 0x00000006)
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intr0 |= 0x00000200;
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return intr0 | intr1;
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}
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