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clk: imx7d: Fix the DDR PLL enable bit

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Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location
of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case.

Fix it accordingly to avoid a kernel hang.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Fabio Estevam 2017-06-06 12:45:54 -03:00 committed by Stephen Boyd
parent 4a5f06a01c
commit b608a89221
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/imx/clk-pllv3.c
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@ -453,7 +453,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
ops = &clk_pllv3_enet_ops;
break;
case IMX_PLLV3_DDR_IMX7:
pll->power_bit = IMX7_ENET_PLL_POWER;
pll->power_bit = IMX7_DDR_PLL_POWER;
ops = &clk_pllv3_av_ops;
break;
default: