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i915: GM45 has GM965-style MCH setup.

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Fixes tiling swizzling mode failures that manifest in glReadPixels().

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Eric Anholt 2008-10-15 00:05:58 -07:00 committed by Dave Airlie
parent 6dbe2772d6
commit b612eda98e
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/drm/i915/i915_gem_tiling.c
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@ -96,7 +96,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
*/ */
swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE;
} else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) { } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) ||
IS_GM45(dev)) {
uint32_t dcc; uint32_t dcc;
/* On 915-945 and GM965, channel interleave by the CPU is /* On 915-945 and GM965, channel interleave by the CPU is
@ -118,7 +119,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
dcc & DCC_CHANNEL_XOR_DISABLE) { dcc & DCC_CHANNEL_XOR_DISABLE) {
swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9; swizzle_y = I915_BIT_6_SWIZZLE_9;
} else if (IS_I965GM(dev)) { } else if (IS_I965GM(dev) || IS_GM45(dev)) {
/* GM965 only does bit 11-based channel /* GM965 only does bit 11-based channel
* randomization * randomization
*/ */