arm64: dts: mediatek: mt7986: reorder properties
[ Upstream commit 7eb133c99fbebc6adb1cbd22c926d42d2bbca648 ] Use order described as preferred in DTS Coding Style. Mostly just move "compatible", "reg" and "ranges" properties. In two nodes also move vendor-prefixed props down. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20240212121620.15035-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Stable-dep-of: 3b449bfd2ff6 ("arm64: dts: mediatek: mt7986: drop invalid properties from ethsys") Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Rafał Miłecki
Greg Kroah-Hartman
parent
7327c4f088
commit
b626cfb651
@ -27,34 +27,34 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x0>;
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device_type = "cpu";
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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device_type = "cpu";
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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device_type = "cpu";
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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device_type = "cpu";
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enable-method = "psci";
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#cooling-cells = <2>;
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};
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};
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@ -131,22 +131,22 @@
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x10000>, /* GICD */
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<0 0x0c080000 0 0x80000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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infracfg: infracfg@10001000 {
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@ -310,9 +310,9 @@
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spi0: spi@1100a000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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reg = <0 0x1100a000 0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_MPLL_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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@ -324,9 +324,9 @@
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spi1: spi@1100b000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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reg = <0 0x1100b000 0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100b000 0 0x100>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_MPLL_D2>,
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<&topckgen CLK_TOP_SPIM_MST_SEL>,
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@ -388,7 +388,6 @@
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};
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thermal: thermal@1100c800 {
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#thermal-sensor-cells = <1>;
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compatible = "mediatek,mt7986-thermal";
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reg = <0 0x1100c800 0 0x800>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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@ -396,30 +395,30 @@
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<&infracfg CLK_INFRA_ADC_26M_CK>,
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<&infracfg CLK_INFRA_ADC_FRC_CK>;
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clock-names = "therm", "auxadc", "adc_32k";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration>;
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nvmem-cell-names = "calibration-data";
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#thermal-sensor-cells = <1>;
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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};
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pcie: pcie@11280000 {
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compatible = "mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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reg = <0x00 0x11280000 0x00 0x4000>;
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reg-names = "pcie-mac";
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ranges = <0x82000000 0x00 0x20000000 0x00
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0x20000000 0x00 0x10000000>;
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x00 0x11280000 0x00 0x4000>;
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reg-names = "pcie-mac";
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0x00 0x20000000 0x00
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0x20000000 0x00 0x10000000>;
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clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
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<&infracfg CLK_INFRA_IPCIE_CK>,
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<&infracfg CLK_INFRA_IPCIER_CK>,
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<&infracfg CLK_INFRA_IPCIEB_CK>;
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clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
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status = "disabled";
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phys = <&pcie_port PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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@ -430,6 +429,8 @@
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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status = "disabled";
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pcie_intc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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@ -440,9 +441,9 @@
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pcie_phy: t-phy {
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compatible = "mediatek,mt7986-tphy",
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"mediatek,generic-tphy-v2";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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pcie_port: pcie-phy@11c00000 {
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@ -467,9 +468,9 @@
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usb_phy: t-phy@11e10000 {
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compatible = "mediatek,mt7986-tphy",
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"mediatek,generic-tphy-v2";
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ranges = <0 0 0x11e10000 0x1700>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x11e10000 0x1700>;
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status = "disabled";
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u2port0: usb-phy@0 {
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@ -497,11 +498,11 @@
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};
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ethsys: syscon@15000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7986-ethsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -578,26 +579,26 @@
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<&topckgen CLK_TOP_SGM_325M_SEL>;
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assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
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<&apmixedsys CLK_APMIXED_SGMPLL>;
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#reset-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
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mediatek,wed-pcie = <&wed_pcie>;
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mediatek,wed = <&wed0>, <&wed1>;
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#reset-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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wifi: wifi@18000000 {
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compatible = "mediatek,mt7986-wmac";
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reg = <0 0x18000000 0 0x1000000>,
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<0 0x10003000 0 0x1000>,
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<0 0x11d10000 0 0x1000>;
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resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
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reset-names = "consys";
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clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
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<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
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clock-names = "mcu", "ap2conn";
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reg = <0 0x18000000 0 0x1000000>,
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<0 0x10003000 0 0x1000>,
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<0 0x11d10000 0 0x1000>;
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interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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