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arm64: dts: mediatek: mt7986: reorder properties

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[ Upstream commit 7eb133c99fbebc6adb1cbd22c926d42d2bbca648 ]

Use order described as preferred in DTS Coding Style. Mostly just move
"compatible", "reg" and "ranges" properties. In two nodes also move
vendor-prefixed props down.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240212121620.15035-1-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Stable-dep-of: 3b449bfd2ff6 ("arm64: dts: mediatek: mt7986: drop invalid properties from ethsys")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Rafał Miłecki 2024-02-12 13:16:19 +01:00 committed by Greg Kroah-Hartman
parent 7327c4f088
commit b626cfb651
1 changed files with 34 additions and 33 deletions
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67
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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@ -27,34 +27,34 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x0>; reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu1: cpu@1 { cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>; reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu2: cpu@2 { cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>; reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu3: cpu@3 { cpu3: cpu@3 {
device_type = "cpu";
enable-method = "psci";
compatible = "arm,cortex-a53"; compatible = "arm,cortex-a53";
reg = <0x3>; reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
}; };
@ -131,22 +131,22 @@
}; };
soc { soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus"; compatible = "simple-bus";
ranges; ranges;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@c000000 { gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3"; compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x10000>, /* GICD */ reg = <0 0x0c000000 0 0x10000>, /* GICD */
<0 0x0c080000 0 0x80000>, /* GICR */ <0 0x0c080000 0 0x80000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */ <0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */ <0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */ <0 0x0c420000 0 0x2000>; /* GICV */
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
}; };
infracfg: infracfg@10001000 { infracfg: infracfg@10001000 {
@ -310,9 +310,9 @@
spi0: spi@1100a000 { spi0: spi@1100a000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x1100a000 0 0x100>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>, clocks = <&topckgen CLK_TOP_MPLL_D2>,
<&topckgen CLK_TOP_SPI_SEL>, <&topckgen CLK_TOP_SPI_SEL>,
@ -324,9 +324,9 @@
spi1: spi@1100b000 { spi1: spi@1100b000 {
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
reg = <0 0x1100b000 0 0x100>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0 0x1100b000 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_MPLL_D2>, clocks = <&topckgen CLK_TOP_MPLL_D2>,
<&topckgen CLK_TOP_SPIM_MST_SEL>, <&topckgen CLK_TOP_SPIM_MST_SEL>,
@ -388,7 +388,6 @@
}; };
thermal: thermal@1100c800 { thermal: thermal@1100c800 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt7986-thermal"; compatible = "mediatek,mt7986-thermal";
reg = <0 0x1100c800 0 0x800>; reg = <0 0x1100c800 0 0x800>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@ -396,30 +395,30 @@
<&infracfg CLK_INFRA_ADC_26M_CK>, <&infracfg CLK_INFRA_ADC_26M_CK>,
<&infracfg CLK_INFRA_ADC_FRC_CK>; <&infracfg CLK_INFRA_ADC_FRC_CK>;
clock-names = "therm", "auxadc", "adc_32k"; clock-names = "therm", "auxadc", "adc_32k";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>; nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration-data"; nvmem-cell-names = "calibration-data";
#thermal-sensor-cells = <1>;
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
}; };
pcie: pcie@11280000 { pcie: pcie@11280000 {
compatible = "mediatek,mt7986-pcie", compatible = "mediatek,mt7986-pcie",
"mediatek,mt8192-pcie"; "mediatek,mt8192-pcie";
reg = <0x00 0x11280000 0x00 0x4000>;
reg-names = "pcie-mac";
ranges = <0x82000000 0x00 0x20000000 0x00
0x20000000 0x00 0x10000000>;
device_type = "pci"; device_type = "pci";
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
reg = <0x00 0x11280000 0x00 0x4000>;
reg-names = "pcie-mac";
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>; bus-range = <0x00 0xff>;
ranges = <0x82000000 0x00 0x20000000 0x00
0x20000000 0x00 0x10000000>;
clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
<&infracfg CLK_INFRA_IPCIE_CK>, <&infracfg CLK_INFRA_IPCIE_CK>,
<&infracfg CLK_INFRA_IPCIER_CK>, <&infracfg CLK_INFRA_IPCIER_CK>,
<&infracfg CLK_INFRA_IPCIEB_CK>; <&infracfg CLK_INFRA_IPCIEB_CK>;
clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
status = "disabled";
phys = <&pcie_port PHY_TYPE_PCIE>; phys = <&pcie_port PHY_TYPE_PCIE>;
phy-names = "pcie-phy"; phy-names = "pcie-phy";
@ -430,6 +429,8 @@
<0 0 0 2 &pcie_intc 1>, <0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>, <0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>; <0 0 0 4 &pcie_intc 3>;
status = "disabled";
pcie_intc: interrupt-controller { pcie_intc: interrupt-controller {
#address-cells = <0>; #address-cells = <0>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
@ -440,9 +441,9 @@
pcie_phy: t-phy { pcie_phy: t-phy {
compatible = "mediatek,mt7986-tphy", compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2"; "mediatek,generic-tphy-v2";
ranges;
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
ranges;
status = "disabled"; status = "disabled";
pcie_port: pcie-phy@11c00000 { pcie_port: pcie-phy@11c00000 {
@ -467,9 +468,9 @@
usb_phy: t-phy@11e10000 { usb_phy: t-phy@11e10000 {
compatible = "mediatek,mt7986-tphy", compatible = "mediatek,mt7986-tphy",
"mediatek,generic-tphy-v2"; "mediatek,generic-tphy-v2";
ranges = <0 0 0x11e10000 0x1700>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0 0x11e10000 0x1700>;
status = "disabled"; status = "disabled";
u2port0: usb-phy@0 { u2port0: usb-phy@0 {
@ -497,11 +498,11 @@
}; };
ethsys: syscon@15000000 { ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7986-ethsys", compatible = "mediatek,mt7986-ethsys",
"syscon"; "syscon";
reg = <0 0x15000000 0 0x1000>; reg = <0 0x15000000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
@ -578,26 +579,26 @@
<&topckgen CLK_TOP_SGM_325M_SEL>; <&topckgen CLK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>; <&apmixedsys CLK_APMIXED_SGMPLL>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
mediatek,ethsys = <&ethsys>; mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
mediatek,wed-pcie = <&wed_pcie>; mediatek,wed-pcie = <&wed_pcie>;
mediatek,wed = <&wed0>, <&wed1>; mediatek,wed = <&wed0>, <&wed1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
wifi: wifi@18000000 { wifi: wifi@18000000 {
compatible = "mediatek,mt7986-wmac"; compatible = "mediatek,mt7986-wmac";
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
<0 0x11d10000 0 0x1000>;
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
reset-names = "consys"; reset-names = "consys";
clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>; <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
clock-names = "mcu", "ap2conn"; clock-names = "mcu", "ap2conn";
reg = <0 0x18000000 0 0x1000000>,
<0 0x10003000 0 0x1000>,
<0 0x11d10000 0 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,