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staging: rtl8188eu: Fix spelling

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rtl8188eu contains some spelling errors in comment lines as well as in
constants. Harmless as they are, they still make the code feel a bit
unclean, which is not something we want in the kernel.

Improve this by fixing typos so they won't catch eyes of future driver
developers anymore.

Signed-off-by: Wolfgang Hartmann <wolfgang.hartmann@siemens.com>
Signed-off-by: Manish Shrestha <manishshrestha2006@gmail.com>
Signed-off-by: Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Valentine Sinitsyn 2017-09-14 18:34:20 -07:00 committed by Greg Kroah-Hartman
parent 008987e5fa
commit b677f4ecf6
5 changed files with 7 additions and 7 deletions
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2
drivers/staging/rtl8188eu/core/rtw_efuse.c
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@ -48,7 +48,7 @@ void Efuse_PowerSwitch(
if (PwrState) { if (PwrState) {
usb_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); usb_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
/* 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid */ /* 1.2V Power: From VDDON with Power Cut(0x0000h[15]), default valid */
tmpV16 = usb_read16(pAdapter, REG_SYS_ISO_CTRL); tmpV16 = usb_read16(pAdapter, REG_SYS_ISO_CTRL);
if (!(tmpV16 & PWC_EV12V)) { if (!(tmpV16 & PWC_EV12V)) {
tmpV16 |= PWC_EV12V; tmpV16 |= PWC_EV12V;

2
drivers/staging/rtl8188eu/core/rtw_mlme.c
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@ -1329,7 +1329,7 @@ void rtw_cpwm_event_callback(struct adapter *padapter, u8 *pbuf)
} }
/* /*
* _rtw_join_timeout_handler - Timeout/faliure handler for CMD JoinBss * _rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss
* @adapter: pointer to struct adapter structure * @adapter: pointer to struct adapter structure
*/ */
void _rtw_join_timeout_handler (unsigned long data) void _rtw_join_timeout_handler (unsigned long data)

4
drivers/staging/rtl8188eu/hal/odm_HWConfig.c
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@ -109,7 +109,7 @@ static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm,
dm_odm->PhyDbgInfo.NumQryPhyStatusCCK++; dm_odm->PhyDbgInfo.NumQryPhyStatusCCK++;
/* (1)Hardware does not provide RSSI for CCK */ /* (1)Hardware does not provide RSSI for CCK */
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */ /* (2)PWDB, Average PWDB calculated by hardware (for rate adaptive) */
cck_highpwr = dm_odm->bCckHighPower; cck_highpwr = dm_odm->bCckHighPower;
@ -223,7 +223,7 @@ static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm,
pPhyInfo->RxSNR[i] = (s32)(pPhyStaRpt->path_rxsnr[i]/2); pPhyInfo->RxSNR[i] = (s32)(pPhyStaRpt->path_rxsnr[i]/2);
dm_odm->PhyDbgInfo.RxSNRdB[i] = (s32)(pPhyStaRpt->path_rxsnr[i]/2); dm_odm->PhyDbgInfo.RxSNRdB[i] = (s32)(pPhyStaRpt->path_rxsnr[i]/2);
} }
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */ /* (2)PWDB, Average PWDB calculated by hardware (for rate adaptive) */
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110; rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110;
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);

2
drivers/staging/rtl8188eu/include/odm.h
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@ -478,7 +478,7 @@ enum odm_operation_mode {
/* ODM_CMNINFO_WM_MODE */ /* ODM_CMNINFO_WM_MODE */
enum odm_wireless_mode { enum odm_wireless_mode {
ODM_WM_UNKNOW = 0x0, ODM_WM_UNKNOWN = 0x0,
ODM_WM_B = BIT(0), ODM_WM_B = BIT(0),
ODM_WM_G = BIT(1), ODM_WM_G = BIT(1),
ODM_WM_A = BIT(2), ODM_WM_A = BIT(2),

4
drivers/staging/rtl8188eu/include/rtl8188e_spec.h
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@ -15,7 +15,7 @@
#ifndef __RTL8188E_SPEC_H__ #ifndef __RTL8188E_SPEC_H__
#define __RTL8188E_SPEC_H__ #define __RTL8188E_SPEC_H__
/* 8192C Regsiter offset definition */ /* 8192C Register offset definition */
#define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */ #define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */
#define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */ #define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */
@ -701,7 +701,7 @@ Current IOREG MAP
#define REG_USB_HRPWM 0xFE58 #define REG_USB_HRPWM 0xFE58
#define REG_USB_HCPWM 0xFE57 #define REG_USB_HCPWM 0xFE57
/* 8192C Regsiter Bit and Content definition */ /* 8192C Register Bit and Content definition */
/* 0x0000h ~ 0x00FFh System Configuration */ /* 0x0000h ~ 0x00FFh System Configuration */
/* 2 SYS_ISO_CTRL */ /* 2 SYS_ISO_CTRL */