net: stmmac: dwmac-qcom-ethqos: Add EMAC3 support
Add the new programming sequence needed for EMAC3 based platforms such as the sc8280xp family. Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Andrew Halaney
Paolo Abeni
parent
030f1d5972
commit
b68376191c
@ -11,6 +11,7 @@
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#define RGMII_IO_MACRO_CONFIG 0x0
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#define SDCC_HC_REG_DLL_CONFIG 0x4
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#define SDCC_TEST_CTL 0x8
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#define SDCC_HC_REG_DDR_CONFIG 0xC
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#define SDCC_HC_REG_DLL_CONFIG2 0x10
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#define SDC4_STATUS 0x14
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@ -49,6 +50,7 @@
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#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21)
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#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27)
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#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30)
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#define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9)
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#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0)
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/* SDCC_HC_REG_DLL_CONFIG2 fields */
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@ -79,6 +81,8 @@ struct ethqos_emac_driver_data {
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const struct ethqos_emac_por *por;
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unsigned int num_por;
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bool rgmii_config_loopback_en;
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bool has_emac3;
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struct dwmac4_addrs dwmac4_addrs;
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};
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struct qcom_ethqos {
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@ -92,6 +96,7 @@ struct qcom_ethqos {
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const struct ethqos_emac_por *por;
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unsigned int num_por;
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bool rgmii_config_loopback_en;
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bool has_emac3;
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};
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static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
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@ -184,6 +189,7 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
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.por = emac_v2_3_0_por,
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.num_por = ARRAY_SIZE(emac_v2_3_0_por),
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.rgmii_config_loopback_en = true,
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.has_emac3 = false,
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};
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static const struct ethqos_emac_por emac_v2_1_0_por[] = {
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@ -199,6 +205,39 @@ static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
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.por = emac_v2_1_0_por,
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.num_por = ARRAY_SIZE(emac_v2_1_0_por),
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.rgmii_config_loopback_en = false,
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.has_emac3 = false,
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};
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static const struct ethqos_emac_por emac_v3_0_0_por[] = {
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{ .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
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{ .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
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{ .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
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{ .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
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{ .offset = SDCC_USR_CTL, .value = 0x00010800 },
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{ .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
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};
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static const struct ethqos_emac_driver_data emac_v3_0_0_data = {
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.por = emac_v3_0_0_por,
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.num_por = ARRAY_SIZE(emac_v3_0_0_por),
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.rgmii_config_loopback_en = false,
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.has_emac3 = true,
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.dwmac4_addrs = {
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.dma_chan = 0x00008100,
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.dma_chan_offset = 0x1000,
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.mtl_chan = 0x00008000,
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.mtl_chan_offset = 0x1000,
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.mtl_ets_ctrl = 0x00008010,
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.mtl_ets_ctrl_offset = 0x1000,
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.mtl_txq_weight = 0x00008018,
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.mtl_txq_weight_offset = 0x1000,
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.mtl_send_slp_cred = 0x0000801c,
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.mtl_send_slp_cred_offset = 0x1000,
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.mtl_high_cred = 0x00008020,
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.mtl_high_cred_offset = 0x1000,
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.mtl_low_cred = 0x00008024,
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.mtl_low_cred_offset = 0x1000,
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},
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};
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static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
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@ -222,11 +261,13 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
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SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
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rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
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0, SDCC_HC_REG_DLL_CONFIG);
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if (!ethqos->has_emac3) {
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rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
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0, SDCC_HC_REG_DLL_CONFIG);
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rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
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0, SDCC_HC_REG_DLL_CONFIG);
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rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
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0, SDCC_HC_REG_DLL_CONFIG);
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}
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/* Wait for CK_OUT_EN clear */
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do {
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@ -261,18 +302,20 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
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SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
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0, SDCC_HC_REG_DLL_CONFIG2);
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if (!ethqos->has_emac3) {
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
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0, SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
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0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
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0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
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BIT(2), SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
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BIT(2), SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
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SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
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SDCC_HC_REG_DLL_CONFIG2);
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
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SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
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SDCC_HC_REG_DLL_CONFIG2);
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}
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return 0;
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}
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@ -327,9 +370,18 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
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RGMII_CONFIG2_RX_PROG_SWAP,
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RGMII_IO_MACRO_CONFIG2);
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/* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
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57, SDCC_HC_REG_DDR_CONFIG);
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/* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
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* in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns
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*/
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if (ethqos->has_emac3) {
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/* 0.9 ns */
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
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115, SDCC_HC_REG_DDR_CONFIG);
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} else {
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/* 1.8 ns */
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
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57, SDCC_HC_REG_DDR_CONFIG);
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}
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
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SDCC_DDR_CONFIG_PRG_DLY_EN,
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SDCC_HC_REG_DDR_CONFIG);
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@ -355,8 +407,15 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
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BIT(6), RGMII_IO_MACRO_CONFIG);
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rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
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0, RGMII_IO_MACRO_CONFIG2);
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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0, RGMII_IO_MACRO_CONFIG2);
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if (ethqos->has_emac3)
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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RGMII_CONFIG2_RX_PROG_SWAP,
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RGMII_IO_MACRO_CONFIG2);
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else
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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0, RGMII_IO_MACRO_CONFIG2);
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/* Write 0x5 to PRG_RCLK_DLY_CODE */
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
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(BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
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@ -389,8 +448,13 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
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RGMII_IO_MACRO_CONFIG);
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rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
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0, RGMII_IO_MACRO_CONFIG2);
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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0, RGMII_IO_MACRO_CONFIG2);
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if (ethqos->has_emac3)
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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RGMII_CONFIG2_RX_PROG_SWAP,
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RGMII_IO_MACRO_CONFIG2);
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else
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rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
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0, RGMII_IO_MACRO_CONFIG2);
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/* Write 0x5 to PRG_RCLK_DLY_CODE */
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rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
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(BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
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@ -433,6 +497,17 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
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SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
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if (ethqos->has_emac3) {
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if (ethqos->speed == SPEED_1000) {
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rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
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rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
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rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
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} else {
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rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL);
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rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
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}
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}
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/* Clear DLL_RST */
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rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
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SDCC_HC_REG_DLL_CONFIG);
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@ -452,7 +527,9 @@ static int ethqos_configure(struct qcom_ethqos *ethqos)
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SDCC_HC_REG_DLL_CONFIG);
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/* Set USR_CTL bit 26 with mask of 3 bits */
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rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL);
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if (!ethqos->has_emac3)
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rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
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SDCC_USR_CTL);
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/* wait for DLL LOCK */
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do {
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@ -547,6 +624,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
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ethqos->por = data->por;
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ethqos->num_por = data->num_por;
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ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
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ethqos->has_emac3 = data->has_emac3;
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ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
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if (IS_ERR(ethqos->rgmii_clk)) {
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@ -566,6 +644,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
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plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
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plat_dat->dump_debug_regs = rgmii_dump;
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plat_dat->has_gmac4 = 1;
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plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
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plat_dat->pmt = 1;
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plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
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if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
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@ -603,6 +682,7 @@ static int qcom_ethqos_remove(struct platform_device *pdev)
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static const struct of_device_id qcom_ethqos_match[] = {
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{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
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{ .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
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{ .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
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{ }
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};
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