[ARM] nommu: add ARM740T core support
This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Hyok S. Choi
Russell King
parent
07e0da78ab
commit
b731c3118d
@ -57,6 +57,7 @@ tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610
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tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710
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tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi
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tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi
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tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi
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tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi
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tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi
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tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi
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@ -75,6 +75,21 @@ config CPU_ARM720T
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Say Y if you want support for the ARM720T processor.
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Otherwise, say N.
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# ARM740T
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config CPU_ARM740T
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bool "Support ARM740T processor" if ARCH_INTEGRATOR
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_CACHE_V3 # although the core is v4t
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select CPU_CP15_MPU
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help
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A 32-bit RISC processor with 8KB cache or 4KB variants,
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write buffer and MPU(Protection Unit) built around
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an ARM7TDMI core.
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Say Y if you want support for the ARM740T processor.
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Otherwise, say N.
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# ARM920T
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config CPU_ARM920T
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bool "Support ARM920T processor"
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@ -436,7 +451,7 @@ comment "Processor Features"
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config ARM_THUMB
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bool "Support Thumb user binaries"
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depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
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depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
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default y
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help
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Say Y if you want to include kernel support for running user space
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@ -473,7 +488,7 @@ config CPU_DCACHE_DISABLE
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config CPU_DCACHE_WRITETHROUGH
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bool "Force write through D-cache"
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depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
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depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
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default y if CPU_ARM925T
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help
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Say Y here to use the data cache in writethrough mode. Unless you
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@ -48,6 +48,7 @@ obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o
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obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o
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obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o
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obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o
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obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o
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obj-$(CONFIG_CPU_ARM920T) += proc-arm920.o
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obj-$(CONFIG_CPU_ARM922T) += proc-arm922.o
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obj-$(CONFIG_CPU_ARM925T) += proc-arm925.o
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174
arch/arm/mm/proc-arm740.S
Normal file
174
arch/arm/mm/proc-arm740.S
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@ -0,0 +1,174 @@
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/*
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* linux/arch/arm/mm/arm740.S: utility functions for ARM740
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*
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* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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.text
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/*
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* cpu_arm740_proc_init()
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* cpu_arm740_do_idle()
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* cpu_arm740_dcache_clean_area()
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* cpu_arm740_switch_mm()
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*
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* These are not required.
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*/
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ENTRY(cpu_arm740_proc_init)
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ENTRY(cpu_arm740_do_idle)
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ENTRY(cpu_arm740_dcache_clean_area)
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ENTRY(cpu_arm740_switch_mm)
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mov pc, lr
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/*
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* cpu_arm740_proc_fin()
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*/
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ENTRY(cpu_arm740_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x3f000000 @ bank/f/lock/s
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bic r0, r0, #0x0000000c @ w-buffer/cache
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mcr p15, 0, r0, c7, c0, 0 @ invalidate cache
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ldmfd sp!, {pc}
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/*
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* cpu_arm740_reset(loc)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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ENTRY(cpu_arm740_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
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mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
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bic ip, ip, #0x0000000c @ ............wc..
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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__INIT
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.type __arm740_setup, #function
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__arm740_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
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mcr p15, 0, r0, c6, c3 @ disable area 3~7
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mcr p15, 0, r0, c6, c4
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mcr p15, 0, r0, c6, c5
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mcr p15, 0, r0, c6, c6
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mcr p15, 0, r0, c6, c7
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mov r0, #0x0000003F @ base = 0, size = 4GB
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mcr p15, 0, r0, c6, c0 @ set area 0, default
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ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
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ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c1 @ set area 1, RAM
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ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
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ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
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mov r0, #0x06
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mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r0, #0x00 @ disable whole write buffer
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#else
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mov r0, #0x02 @ Region 1 write bufferred
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#endif
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mcr p15, 0, r0, c3, c0
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mov r0, #0x10000
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sub r0, r0, #1 @ r0 = 0xffff
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mcr p15, 0, r0, c5, c0 @ all read/write access
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mrc p15, 0, r0, c1, c0 @ get control register
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bic r0, r0, #0x3F000000 @ set to standard caching mode
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@ need some benchmark
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orr r0, r0, #0x0000000d @ MPU/Cache/WB
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mov pc, lr
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.size __arm740_setup, . - __arm740_setup
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__INITDATA
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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.type arm740_processor_functions, #object
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ENTRY(arm740_processor_functions)
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.word v4t_late_abort
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.word cpu_arm740_proc_init
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.word cpu_arm740_proc_fin
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.word cpu_arm740_reset
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.word cpu_arm740_do_idle
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.word cpu_arm740_dcache_clean_area
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.word cpu_arm740_switch_mm
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.word 0 @ cpu_*_set_pte
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.size arm740_processor_functions, . - arm740_processor_functions
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.section ".rodata"
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.type cpu_arch_name, #object
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cpu_arch_name:
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.asciz "armv4"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name:
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.asciz "v4"
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.size cpu_elf_name, . - cpu_elf_name
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.type cpu_arm740_name, #object
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cpu_arm740_name:
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.ascii "ARM740T"
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.size cpu_arm740_name, . - cpu_arm740_name
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.align
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.section ".proc.info.init", #alloc, #execinstr
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.type __arm740_proc_info,#object
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__arm740_proc_info:
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.long 0x41807400
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.long 0xfffffff0
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.long 0
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b __arm740_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
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.long cpu_arm740_name
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.long arm740_processor_functions
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.long 0
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.long 0
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.long v3_cache_fns @ cache model
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.size __arm740_proc_info, . - __arm740_proc_info
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@ -25,7 +25,8 @@
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#undef _CACHE
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#undef MULTI_CACHE
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#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
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#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) || \
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defined(CONFIG_CPU_ARM740T)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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@ -57,6 +57,14 @@
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# define CPU_NAME cpu_arm720
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM740T
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_arm740
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# endif
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# endif
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# ifdef CONFIG_CPU_ARM920T
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# ifdef CPU_NAME
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# undef MULTI_CPU
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