mt76x2: dfs: add sw pattern detector
Add sw DFS pattern detector support for mt76x2 based devices. Dfs pattern supported: - short pulse radar patterns - staggered radar patterns Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Lorenzo Bianconi
Kalle Valo
parent
1fc9bc9ab5
commit
b7384e4e0d
@ -159,9 +159,57 @@ static void mt76x2_dfs_set_capture_mode_ctrl(struct mt76x2_dev *dev,
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mt76_wr(dev, MT_BBP(DFS, 36), data);
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}
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static void mt76x2_dfs_seq_pool_put(struct mt76x2_dev *dev,
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struct mt76x2_dfs_sequence *seq)
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{
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struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;
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list_add(&seq->head, &dfs_pd->seq_pool);
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}
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static
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struct mt76x2_dfs_sequence *mt76x2_dfs_seq_pool_get(struct mt76x2_dev *dev)
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{
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struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;
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struct mt76x2_dfs_sequence *seq;
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if (list_empty(&dfs_pd->seq_pool)) {
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seq = devm_kzalloc(dev->mt76.dev, sizeof(*seq), GFP_ATOMIC);
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} else {
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seq = list_first_entry(&dfs_pd->seq_pool,
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struct mt76x2_dfs_sequence,
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head);
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list_del(&seq->head);
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}
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return seq;
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}
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static int mt76x2_dfs_get_multiple(int val, int frac, int margin)
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{
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int remainder, factor;
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if (!frac)
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return 0;
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if (abs(val - frac) <= margin)
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return 1;
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factor = val / frac;
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remainder = val % frac;
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if (remainder > margin) {
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if ((frac - remainder) <= margin)
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factor++;
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else
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factor = 0;
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}
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return factor;
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}
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static void mt76x2_dfs_detector_reset(struct mt76x2_dev *dev)
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{
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struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;
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struct mt76x2_dfs_sequence *seq, *tmp_seq;
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int i;
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/* reset hw detector */
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@ -172,6 +220,11 @@ static void mt76x2_dfs_detector_reset(struct mt76x2_dev *dev)
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dfs_pd->event_rb[i].h_rb = 0;
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dfs_pd->event_rb[i].t_rb = 0;
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}
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list_for_each_entry_safe(seq, tmp_seq, &dfs_pd->sequences, head) {
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list_del_init(&seq->head);
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mt76x2_dfs_seq_pool_put(dev, seq);
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}
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}
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static bool mt76x2_dfs_check_chirp(struct mt76x2_dev *dev)
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@ -374,11 +427,145 @@ static void mt76x2_dfs_queue_event(struct mt76x2_dev *dev,
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MT_DFS_EVENT_BUFLEN);
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}
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static int mt76x2_dfs_create_sequence(struct mt76x2_dev *dev,
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struct mt76x2_dfs_event *event,
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u16 cur_len)
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{
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struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;
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struct mt76x2_dfs_sw_detector_params *sw_params;
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u32 width_delta, with_sum, factor, cur_pri;
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struct mt76x2_dfs_sequence seq, *seq_p;
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struct mt76x2_dfs_event_rb *event_rb;
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struct mt76x2_dfs_event *cur_event;
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int i, j, end, pri;
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event_rb = event->engine == 2 ? &dfs_pd->event_rb[1]
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: &dfs_pd->event_rb[0];
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i = mt76_decr(event_rb->t_rb, MT_DFS_EVENT_BUFLEN);
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end = mt76_decr(event_rb->h_rb, MT_DFS_EVENT_BUFLEN);
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while (i != end) {
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cur_event = &event_rb->data[i];
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with_sum = event->width + cur_event->width;
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sw_params = &dfs_pd->sw_dpd_params;
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switch (dev->dfs_pd.region) {
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case NL80211_DFS_FCC:
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case NL80211_DFS_JP:
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if (with_sum < 600)
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width_delta = 8;
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else
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width_delta = with_sum >> 3;
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break;
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case NL80211_DFS_ETSI:
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if (event->engine == 2)
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width_delta = with_sum >> 6;
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else if (with_sum < 620)
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width_delta = 24;
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else
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width_delta = 8;
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break;
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case NL80211_DFS_UNSET:
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default:
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return -EINVAL;
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}
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pri = event->ts - cur_event->ts;
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if (abs(event->width - cur_event->width) > width_delta ||
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pri < sw_params->min_pri)
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goto next;
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if (pri > sw_params->max_pri)
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break;
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seq.pri = event->ts - cur_event->ts;
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seq.first_ts = cur_event->ts;
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seq.last_ts = event->ts;
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seq.engine = event->engine;
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seq.count = 2;
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j = mt76_decr(i, MT_DFS_EVENT_BUFLEN);
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while (j != end) {
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cur_event = &event_rb->data[j];
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cur_pri = event->ts - cur_event->ts;
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factor = mt76x2_dfs_get_multiple(cur_pri, seq.pri,
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sw_params->pri_margin);
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if (factor > 0) {
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seq.first_ts = cur_event->ts;
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seq.count++;
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}
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j = mt76_decr(j, MT_DFS_EVENT_BUFLEN);
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}
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if (seq.count <= cur_len)
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goto next;
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seq_p = mt76x2_dfs_seq_pool_get(dev);
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if (!seq_p)
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return -ENOMEM;
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*seq_p = seq;
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INIT_LIST_HEAD(&seq_p->head);
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list_add(&seq_p->head, &dfs_pd->sequences);
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next:
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i = mt76_decr(i, MT_DFS_EVENT_BUFLEN);
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}
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return 0;
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}
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static u16 mt76x2_dfs_add_event_to_sequence(struct mt76x2_dev *dev,
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struct mt76x2_dfs_event *event)
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{
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struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;
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struct mt76x2_dfs_sw_detector_params *sw_params;
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struct mt76x2_dfs_sequence *seq, *tmp_seq;
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u16 max_seq_len = 0;
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u32 factor, pri;
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sw_params = &dfs_pd->sw_dpd_params;
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list_for_each_entry_safe(seq, tmp_seq, &dfs_pd->sequences, head) {
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if (event->ts > seq->first_ts + MT_DFS_SEQUENCE_WINDOW) {
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list_del_init(&seq->head);
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mt76x2_dfs_seq_pool_put(dev, seq);
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continue;
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}
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if (event->engine != seq->engine)
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continue;
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pri = event->ts - seq->last_ts;
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factor = mt76x2_dfs_get_multiple(pri, seq->pri,
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sw_params->pri_margin);
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if (factor > 0) {
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seq->last_ts = event->ts;
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seq->count++;
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max_seq_len = max_t(u16, max_seq_len, seq->count);
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}
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}
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return max_seq_len;
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}
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static bool mt76x2_dfs_check_detection(struct mt76x2_dev *dev)
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{
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struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;
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struct mt76x2_dfs_sequence *seq;
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if (list_empty(&dfs_pd->sequences))
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return false;
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list_for_each_entry(seq, &dfs_pd->sequences, head) {
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if (seq->count > MT_DFS_SEQUENCE_TH)
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return true;
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}
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return false;
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}
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static void mt76x2_dfs_add_events(struct mt76x2_dev *dev)
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{
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struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;
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struct mt76x2_dfs_event event;
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int i;
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int i, seq_len;
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/* disable debug mode */
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mt76x2_dfs_set_capture_mode_ctrl(dev, false);
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@ -393,6 +580,9 @@ static void mt76x2_dfs_add_events(struct mt76x2_dev *dev)
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if (!mt76x2_dfs_check_event(dev, &event))
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continue;
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seq_len = mt76x2_dfs_add_event_to_sequence(dev, &event);
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mt76x2_dfs_create_sequence(dev, &event, seq_len);
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mt76x2_dfs_queue_event(dev, &event);
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}
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mt76x2_dfs_set_capture_mode_ctrl(dev, true);
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@ -433,9 +623,19 @@ static void mt76x2_dfs_tasklet(unsigned long arg)
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if (time_is_before_jiffies(dfs_pd->last_sw_check +
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MT_DFS_SW_TIMEOUT)) {
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bool radar_detected;
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dfs_pd->last_sw_check = jiffies;
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mt76x2_dfs_add_events(dev);
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radar_detected = mt76x2_dfs_check_detection(dev);
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if (radar_detected) {
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/* sw detector rx radar pattern */
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ieee80211_radar_detected(dev->mt76.hw);
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mt76x2_dfs_detector_reset(dev);
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return;
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}
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mt76x2_dfs_check_event_window(dev);
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}
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@ -472,6 +672,32 @@ out:
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mt76x2_irq_enable(dev, MT_INT_GPTIMER);
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}
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static void mt76x2_dfs_init_sw_detector(struct mt76x2_dev *dev)
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{
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struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;
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switch (dev->dfs_pd.region) {
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case NL80211_DFS_FCC:
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dfs_pd->sw_dpd_params.max_pri = MT_DFS_FCC_MAX_PRI;
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dfs_pd->sw_dpd_params.min_pri = MT_DFS_FCC_MIN_PRI;
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dfs_pd->sw_dpd_params.pri_margin = MT_DFS_PRI_MARGIN;
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break;
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case NL80211_DFS_ETSI:
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dfs_pd->sw_dpd_params.max_pri = MT_DFS_ETSI_MAX_PRI;
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dfs_pd->sw_dpd_params.min_pri = MT_DFS_ETSI_MIN_PRI;
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dfs_pd->sw_dpd_params.pri_margin = MT_DFS_PRI_MARGIN << 2;
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break;
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case NL80211_DFS_JP:
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dfs_pd->sw_dpd_params.max_pri = MT_DFS_JP_MAX_PRI;
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dfs_pd->sw_dpd_params.min_pri = MT_DFS_JP_MIN_PRI;
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dfs_pd->sw_dpd_params.pri_margin = MT_DFS_PRI_MARGIN;
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break;
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case NL80211_DFS_UNSET:
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default:
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break;
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}
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}
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static void mt76x2_dfs_set_bbp_params(struct mt76x2_dev *dev)
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{
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u32 data;
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@ -594,6 +820,7 @@ void mt76x2_dfs_init_params(struct mt76x2_dev *dev)
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if ((chandef->chan->flags & IEEE80211_CHAN_RADAR) &&
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dev->dfs_pd.region != NL80211_DFS_UNSET) {
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mt76x2_dfs_init_sw_detector(dev);
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mt76x2_dfs_set_bbp_params(dev);
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/* enable debug mode */
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mt76x2_dfs_set_capture_mode_ctrl(dev, true);
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@ -618,6 +845,8 @@ void mt76x2_dfs_init_detector(struct mt76x2_dev *dev)
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{
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struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;
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INIT_LIST_HEAD(&dfs_pd->sequences);
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INIT_LIST_HEAD(&dfs_pd->seq_pool);
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dfs_pd->region = NL80211_DFS_UNSET;
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dfs_pd->last_sw_check = jiffies;
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tasklet_init(&dfs_pd->dfs_tasklet, mt76x2_dfs_tasklet,
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@ -37,7 +37,17 @@
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#define MT_DFS_EVENT_LOOP 64
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#define MT_DFS_SW_TIMEOUT (HZ / 20)
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#define MT_DFS_EVENT_WINDOW (HZ / 5)
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#define MT_DFS_SEQUENCE_WINDOW (200 * (1 << 20))
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#define MT_DFS_EVENT_TIME_MARGIN 2000
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#define MT_DFS_PRI_MARGIN 4
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#define MT_DFS_SEQUENCE_TH 6
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#define MT_DFS_FCC_MAX_PRI ((28570 << 1) + 1000)
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#define MT_DFS_FCC_MIN_PRI (3000 - 2)
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#define MT_DFS_JP_MAX_PRI ((80000 << 1) + 1000)
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#define MT_DFS_JP_MIN_PRI (28500 - 2)
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#define MT_DFS_ETSI_MAX_PRI (133333 + 125000 + 117647 + 1000)
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#define MT_DFS_ETSI_MIN_PRI (4500 - 20)
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struct mt76x2_radar_specs {
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u8 mode;
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@ -73,6 +83,15 @@ struct mt76x2_dfs_event_rb {
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int h_rb, t_rb;
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};
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struct mt76x2_dfs_sequence {
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struct list_head head;
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u32 first_ts;
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u32 last_ts;
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u32 pri;
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u16 count;
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u8 engine;
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};
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struct mt76x2_dfs_hw_pulse {
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u8 engine;
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u32 period;
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@ -81,6 +100,12 @@ struct mt76x2_dfs_hw_pulse {
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u32 burst;
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};
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struct mt76x2_dfs_sw_detector_params {
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u32 min_pri;
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u32 max_pri;
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u32 pri_margin;
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};
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struct mt76x2_dfs_engine_stats {
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u32 hw_pattern;
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u32 hw_pulse_discarded;
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@ -92,7 +117,12 @@ struct mt76x2_dfs_pattern_detector {
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u8 chirp_pulse_cnt;
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u32 chirp_pulse_ts;
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struct mt76x2_dfs_sw_detector_params sw_dpd_params;
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struct mt76x2_dfs_event_rb event_rb[2];
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struct list_head sequences;
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struct list_head seq_pool;
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unsigned long last_sw_check;
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u32 last_event_ts;
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