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arm64: ZynqMP DT changes for 6.9

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dt-bindings:
 - Describe firmware for Versal NET
 - Describe all firmware child nodes
 - Align versal-fpga node name with dt schema
 - Describe k26 rev2 and kv260
 
 DTs:
 - Align firmware node with dt schema
 - Add an optee node
 - Describe reset for CANs
 - Update ECAM size to discover up to 256 buses
 - Describe assigned-clocks for uarts
 - Add u-boot node
 - Comment SMMU entries
 - Align dwc3 nodes with dt schema
 - Rename i2c groups to match dt schema
 - Small DT updates (comments)
 - Fix default clock frequency for si570 (zcu102, zcu106)
 - Add output-enable pins and cover MIO38 (SOM)
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCZdyDIwAKCRDKSWXLKUoM
 IRTlAKCBnBVaSTKA2VR6roEHzjsg2ri+jgCfcnNnm1wc5KdnKsW17kHmKGjTFaI=
 =0Qlr
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXhzg8ACgkQYKtH/8kJ
 UieZLRAA2UvwLSnLB49ByEj1y0jLCqjWBxAdivzi/hAq3XTw7+CljUupWBggYIYG
 Y3P1Md26+LbUNvlIeEMP/HCznJC3tQiuVmPtpGAJXJoRbFNgpSxqn76Q+FQ03mLc
 UBAtybk9DXxqxqx5lIYbLQ5CtZMPdUObN+kXksu/Uw27vUVjDWsKOIfwpK+D04aj
 req2R6dWEp6diP94++oH33PQPn3i5EeAXM8nN3mDpuS+ffLqdnAhvhb3s2xHNi8m
 B+gpGP59lTRC0AGmoh9TJo+ErEogMDW5PTA3GKlhlZVXNFxkyA2W1tkiVyhvBfu9
 3TrC+pmZeofB3n0d68ekJ5gt8TNeecjvM09DgO6K7imPLXkR5aMagyx+WJHU06O6
 0naQzCYwsMQuDKnspFWYviszk648fvQqNpcU5A/rHkm2mFUTFGV2ZNLRh9YA6UfO
 vRDr7iIQ3N3F0kDmiPBbKoMKEu5o+WFWc8YgjnHbLTThalsGACzHYYyFjQdcnkh7
 9cnG9qdb/dduFFtrp54Uk2I/DF+tBTaiYWvWCHbNDw23nu5u4mLS3t9ORhXPyg7k
 KKikhRXhCjab2hFMGtC7zhiUnGpoK4BPckJSYPCXVNM55qkZO0PgKr7W5Ieor0BM
 XRK4UqbkX8e0knxF0YIGsESno6876hrL1T5E+jO4ldhNUR9nu7U=
 =dkX9
 -----END PGP SIGNATURE-----

Merge tag 'zynqmp-dt-for-6.9' of https://github.com/Xilinx/linux-xlnx into soc/dt

arm64: ZynqMP DT changes for 6.9

dt-bindings:
- Describe firmware for Versal NET
- Describe all firmware child nodes
- Align versal-fpga node name with dt schema
- Describe k26 rev2 and kv260

DTs:
- Align firmware node with dt schema
- Add an optee node
- Describe reset for CANs
- Update ECAM size to discover up to 256 buses
- Describe assigned-clocks for uarts
- Add u-boot node
- Comment SMMU entries
- Align dwc3 nodes with dt schema
- Rename i2c groups to match dt schema
- Small DT updates (comments)
- Fix default clock frequency for si570 (zcu102, zcu106)
- Add output-enable pins and cover MIO38 (SOM)

* tag 'zynqmp-dt-for-6.9' of https://github.com/Xilinx/linux-xlnx: (21 commits)
  dt-bindings: firmware: xilinx: Describe soc-nvmem subnode
  dt-bindings: soc: xilinx: Add support for KV260 CC
  dt-bindings: soc: xilinx: Add support for K26 rev2 SOMs
  arm64: zynqmp: Align usb clock nodes with binding
  arm64: zynqmp: Comment all smmu entries
  arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp
  arm64: zynqmp: Disable Tri-state for MIO38 Pin
  arm64: zynqmp: Remove incorrect comment from kv260s
  arm64: zynqmp: Introduce u-boot options node with bootscr-address
  arm64: zynqmp: Fix comment to be aligned with board name.
  arm64: zynqmp: Update ECAM size to discover up to 256 buses
  arm64: zynqmp: Describe assigned-clocks for uarts
  arm64: zynqmp: Setup default si570 frequency to 156.25MHz
  arm64: zynqmp: Add resets property for CAN nodes
  arm64: zynqmp: Add an OP-TEE node to the device tree
  arm64: zynqmp: Add output-enable pins to SOMs
  arm64: zynqmp: Rename zynqmp-power node to power-management
  dt-bindings: firmware: xilinx: Sort node names (clock-controller)
  dt-bindings: firmware: xilinx: Describe missing child nodes
  dt-bindings: firmware: xilinx: Fix versal-fpga node name
  ...

Link: https://lore.kernel.org/r/CAHTX3dLEoFMTGg1Q4+OuOwWYd8N73YBTXki8Vvj3cGHUpLJ0=A@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-03-01 13:46:06 +01:00
commit b797b9cde4
17 changed files with 295 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

96
Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
View File

@ -26,6 +26,12 @@ properties:
- description: For implementations complying for Versal.
const: xlnx,versal-firmware
- description: For implementations complying for Versal NET.
items:
- enum:
- xlnx,versal-net-firmware
- const: xlnx,versal-firmware
method:
description: |
The method of calling the PM-API firmware layer.
@ -41,7 +47,53 @@ properties:
"#power-domain-cells":
const: 1
versal_fpga:
clock-controller:
$ref: /schemas/clock/xlnx,versal-clk.yaml#
description: The clock controller is a hardware block of Xilinx versal
clock tree. It reads required input clock frequencies from the devicetree
and acts as clock provider for all clock consumers of PS clocks.list of
clock specifiers which are external input clocks to the given clock
controller.
type: object
gpio:
$ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
description: The gpio node describes connect to PS_MODE pins via firmware
interface.
type: object
soc-nvmem:
$ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
description: The ZynqMP MPSoC provides access to the hardware related data
like SOC revision, IDCODE and specific purpose efuses.
type: object
pcap:
$ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
configure the Programmable Logic (PL). The configuration uses the
firmware interface.
type: object
pinctrl:
$ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
description: The pinctrl node provides access to pinconfig and pincontrol
functionality available in firmware.
type: object
power-management:
$ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
description: The zynqmp-power node describes the power management
configurations. It will control remote suspend/shutdown interfaces.
type: object
reset-controller:
$ref: /schemas/reset/xlnx,zynqmp-reset.yaml#
description: The reset-controller node describes connection to the reset
functionality via firmware interface.
type: object
versal-fpga:
$ref: /schemas/fpga/xlnx,versal-fpga.yaml#
description: Compatible of the FPGA device.
type: object
@ -53,15 +105,6 @@ properties:
vector.
type: object
clock-controller:
$ref: /schemas/clock/xlnx,versal-clk.yaml#
description: The clock controller is a hardware block of Xilinx versal
clock tree. It reads required input clock frequencies from the devicetree
and acts as clock provider for all clock consumers of PS clocks.list of
clock specifiers which are external input clocks to the given clock
controller.
type: object
required:
- compatible
@ -73,7 +116,38 @@ examples:
firmware {
zynqmp_firmware: zynqmp-firmware {
#power-domain-cells = <1>;
soc-nvmem {
compatible = "xlnx,zynqmp-nvmem-fw";
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
};
};
gpio {
compatible = "xlnx,zynqmp-gpio-modepin";
gpio-controller;
#gpio-cells = <2>;
};
pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
};
power-management {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
};
};
sata {
@ -84,7 +158,7 @@ examples:
compatible = "xlnx,versal-firmware";
method = "smc";
versal_fpga: versal_fpga {
versal_fpga: versal-fpga {
compatible = "xlnx,versal-fpga";
};

2
Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
View File

@ -26,7 +26,7 @@ additionalProperties: false
examples:
- |
versal_fpga: versal_fpga {
versal_fpga: versal-fpga {
compatible = "xlnx,versal-fpga";
};

70
Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
View File

@ -117,20 +117,70 @@ properties:
- const: xlnx,zynqmp
- description: Xilinx Kria SOMs
minItems: 3
items:
- const: xlnx,zynqmp-sm-k26-rev1
- const: xlnx,zynqmp-sm-k26-revB
- const: xlnx,zynqmp-sm-k26-revA
- const: xlnx,zynqmp-sm-k26
- const: xlnx,zynqmp
enum:
- xlnx,zynqmp-sm-k26-rev2
- xlnx,zynqmp-sm-k26-rev1
- xlnx,zynqmp-sm-k26-revB
- xlnx,zynqmp-sm-k26-revA
- xlnx,zynqmp-sm-k26
- xlnx,zynqmp
allOf:
- contains:
const: xlnx,zynqmp
- contains:
const: xlnx,zynqmp-sm-k26
- description: Xilinx Kria SOMs (starter)
minItems: 3
items:
- const: xlnx,zynqmp-smk-k26-rev1
- const: xlnx,zynqmp-smk-k26-revB
- const: xlnx,zynqmp-smk-k26-revA
- const: xlnx,zynqmp-smk-k26
- const: xlnx,zynqmp
enum:
- xlnx,zynqmp-smk-k26-rev2
- xlnx,zynqmp-smk-k26-rev1
- xlnx,zynqmp-smk-k26-revB
- xlnx,zynqmp-smk-k26-revA
- xlnx,zynqmp-smk-k26
- xlnx,zynqmp
allOf:
- contains:
const: xlnx,zynqmp
- contains:
const: xlnx,zynqmp-smk-k26
- description: Xilinx Kria SOM KV260 revA/Y/Z
minItems: 3
items:
enum:
- xlnx,zynqmp-sk-kv260-revA
- xlnx,zynqmp-sk-kv260-revY
- xlnx,zynqmp-sk-kv260-revZ
- xlnx,zynqmp-sk-kv260
- xlnx,zynqmp
allOf:
- contains:
const: xlnx,zynqmp-sk-kv260-revA
- contains:
const: xlnx,zynqmp-sk-kv260
- contains:
const: xlnx,zynqmp
- description: Xilinx Kria SOM KV260 rev2/1/B
minItems: 3
items:
enum:
- xlnx,zynqmp-sk-kv260-rev2
- xlnx,zynqmp-sk-kv260-rev1
- xlnx,zynqmp-sk-kv260-revB
- xlnx,zynqmp-sk-kv260
- xlnx,zynqmp
allOf:
- contains:
const: xlnx,zynqmp-sk-kv260-revB
- contains:
const: xlnx,zynqmp-sk-kv260
- contains:
const: xlnx,zynqmp
- description: AMD MicroBlaze V (QEMU)
items:

16
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
View File

@ -230,18 +230,30 @@
&uart0 {
clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk UART0_REF>;
};
&uart1 {
clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk UART1_REF>;
};
&usb0 {
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&dwc3_0 {
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
clocks = <&zynqmp_clk USB3_DUAL_REF>;
};
&usb1 {
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&dwc3_1 {
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
clocks = <&zynqmp_clk USB3_DUAL_REF>;
};
&watchdog0 {

36
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
View File

@ -139,7 +139,7 @@
bus-width = <4>;
};
&gem3 { /* required by spec */
&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
@ -166,9 +166,28 @@
};
};
&pinctrl0 { /* required by spec */
&pinctrl0 {
status = "okay";
pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@ -185,6 +204,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
@ -207,7 +227,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
@ -236,6 +256,7 @@
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
output-enable;
low-power-disable;
};
@ -243,6 +264,7 @@
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
output-enable;
low-power-enable;
};
@ -251,6 +273,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
@ -281,6 +304,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@ -319,6 +343,12 @@
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";

37
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
View File

@ -94,6 +94,7 @@
pinctrl-0 = <&pinctrl_usb0_default>;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
assigned-clock-rates = <250000000>, <20000000>;
};
&dwc3_0 {
@ -122,7 +123,7 @@
bus-width = <4>;
};
&gem3 { /* required by spec */
&gem3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
@ -149,9 +150,28 @@
};
};
&pinctrl0 { /* required by spec */
&pinctrl0 {
status = "okay";
pinctrl_gpio0_default: gpio0-default {
conf {
groups = "gpio0_38_grp";
bias-pull-up;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_38_grp";
function = "gpio0";
};
conf-tx {
pins = "MIO38";
bias-disable;
output-enable;
};
};
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@ -168,6 +188,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
output-enable;
};
mux {
@ -190,7 +211,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
@ -219,6 +240,7 @@
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
output-enable;
low-power-disable;
};
@ -226,6 +248,7 @@
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
output-enable;
low-power-enable;
};
@ -234,6 +257,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
output-enable;
};
mux-mdio {
@ -264,6 +288,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@ -302,6 +327,12 @@
};
};
&gpio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";

2
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
View File

@ -148,7 +148,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_36_grp", "gpio0_37_grp";
function = "gpio0";

2
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
View File

@ -219,7 +219,7 @@
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_6_grp", "gpio0_7_grp";
function = "gpio0";

4
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
View File

@ -125,7 +125,7 @@
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_74_grp", "gpio0_75_grp";
function = "gpio0";
@ -152,7 +152,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_76_grp", "gpio0_77_grp";
function = "gpio0";

2
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
View File

@ -275,7 +275,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_4_grp", "gpio0_5_grp";
function = "gpio0";

6
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
View File

@ -603,7 +603,7 @@
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
clock-frequency = <148500000>;
clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
@ -689,7 +689,7 @@
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
@ -716,7 +716,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";

2
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
View File

@ -272,7 +272,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";

2
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
View File

@ -284,7 +284,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";

6
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
View File

@ -605,7 +605,7 @@
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
clock-frequency = <148500000>;
clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
@ -700,7 +700,7 @@
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
@ -727,7 +727,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
View File

@ -589,7 +589,7 @@
};
};
pinctrl_i2c0_gpio: i2c0-gpio {
pinctrl_i2c0_gpio: i2c0-gpio-grp {
mux {
groups = "gpio0_14_grp", "gpio0_15_grp";
function = "gpio0";
@ -616,7 +616,7 @@
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
pinctrl_i2c1_gpio: i2c1-gpio-grp {
mux {
groups = "gpio0_16_grp", "gpio0_17_grp";
function = "gpio0";

2
arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZC1275
* dts file for Xilinx ZynqMP ZCU1275
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*

85
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View File

@ -24,6 +24,13 @@
#address-cells = <2>;
#size-cells = <2>;
options {
u-boot {
compatible = "u-boot,config";
bootscr-address = /bits/ 64 <0x20000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -180,13 +187,18 @@
};
firmware {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
};
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <1>;
method = "smc";
bootph-all;
zynqmp_power: zynqmp-power {
zynqmp_power: power-management {
bootph-all;
compatible = "xlnx,zynqmp-power";
interrupt-parent = <&gic>;
@ -281,6 +293,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;
power-domains = <&zynqmp_firmware PD_CAN_0>;
};
@ -293,6 +306,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;
power-domains = <&zynqmp_firmware PD_CAN_1>;
};
@ -326,7 +340,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e8>;
/* iommus = <&smmu 0x14e8>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -339,7 +353,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e9>;
/* iommus = <&smmu 0x14e9>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -352,7 +366,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ea>;
/* iommus = <&smmu 0x14ea>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -365,7 +379,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14eb>;
/* iommus = <&smmu 0x14eb>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -378,7 +392,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ec>;
/* iommus = <&smmu 0x14ec>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -391,7 +405,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ed>;
/* iommus = <&smmu 0x14ed>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -404,7 +418,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ee>;
/* iommus = <&smmu 0x14ee>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -417,7 +431,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ef>;
/* iommus = <&smmu 0x14ef>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@ -462,7 +476,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x868>;
/* iommus = <&smmu 0x868>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -475,7 +489,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x869>;
/* iommus = <&smmu 0x869>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -488,7 +502,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86a>;
/* iommus = <&smmu 0x86a>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -501,7 +515,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86b>;
/* iommus = <&smmu 0x86b>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -514,7 +528,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86c>;
/* iommus = <&smmu 0x86c>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -527,7 +541,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86d>;
/* iommus = <&smmu 0x86d>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -540,7 +554,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86e>;
/* iommus = <&smmu 0x86e>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -553,7 +567,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
iommus = <&smmu 0x86f>;
/* iommus = <&smmu 0x86f>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@ -573,7 +587,7 @@
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
iommus = <&smmu 0x872>;
/* iommus = <&smmu 0x872>; */
power-domains = <&zynqmp_firmware PD_NAND>;
};
@ -585,7 +599,7 @@
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
iommus = <&smmu 0x874>;
/* iommus = <&smmu 0x874>; */
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
reset-names = "gem0_rst";
@ -599,7 +613,7 @@
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
iommus = <&smmu 0x875>;
/* iommus = <&smmu 0x875>; */
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
reset-names = "gem1_rst";
@ -613,7 +627,7 @@
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
iommus = <&smmu 0x876>;
/* iommus = <&smmu 0x876>; */
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
reset-names = "gem2_rst";
@ -627,7 +641,7 @@
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
iommus = <&smmu 0x877>;
/* iommus = <&smmu 0x877>; */
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
reset-names = "gem3_rst";
@ -689,7 +703,7 @@
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
<0x80 0x00000000 0x0 0x1000000>;
<0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
@ -699,7 +713,7 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
iommus = <&smmu 0x4d0>;
/* iommus = <&smmu 0x4d0>; */
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
@ -720,7 +734,7 @@
<0x0 0xc0000000 0x0 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
iommus = <&smmu 0x873>;
/* iommus = <&smmu 0x873>; */
power-domains = <&zynqmp_firmware PD_QSPI>;
};
@ -752,8 +766,7 @@
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
<&smmu 0x4c2>, <&smmu 0x4c3>;
/* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
};
sdhci0: mmc@ff160000 {
@ -764,7 +777,7 @@
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
iommus = <&smmu 0x870>;
/* iommus = <&smmu 0x870>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
@ -779,7 +792,7 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
iommus = <&smmu 0x871>;
/* iommus = <&smmu 0x871>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
@ -912,6 +925,7 @@
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9d0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
@ -922,14 +936,15 @@
dwc3_0: usb@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "host", "peripheral", "otg";
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "bus_early", "ref";
iommus = <&smmu 0x860>;
clock-names = "ref";
/* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
snps,resume-hs-terminations;
/* dma-coherent; */
@ -942,6 +957,7 @@
status = "disabled";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9e0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
@ -951,14 +967,15 @@
dwc3_1: usb@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "host", "peripheral", "otg";
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "bus_early", "ref";
iommus = <&smmu 0x861>;
clock-names = "ref";
/* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
snps,resume-hs-terminations;
/* dma-coherent; */
@ -1018,6 +1035,7 @@
interrupt-parent = <&gic>;
clock-names = "axi_clk";
power-domains = <&zynqmp_firmware PD_DP>;
/* iommus = <&smmu 0xce4>; */
#dma-cells = <1>;
};
@ -1032,6 +1050,7 @@
reg-names = "dp", "blend", "av_buf", "aud";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
/* iommus = <&smmu 0xce3>; */
clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;