drm/amdgpu: enable vce powergating
Enable VCE dpm and powergating. VCE dpm dynamically scales the VCE clocks on demand. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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@ -1509,6 +1509,7 @@ struct amdgpu_dpm_funcs {
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int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
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bool (*vblank_too_short)(struct amdgpu_device *adev);
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void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
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void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
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void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
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void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
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u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
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@ -2182,6 +2183,7 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
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#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
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#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
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#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
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#define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
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#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
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#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
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#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
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@ -656,19 +656,27 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
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void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
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{
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if (enable) {
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if (adev->pm.funcs->powergate_vce) {
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mutex_lock(&adev->pm.mutex);
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adev->pm.dpm.vce_active = true;
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/* XXX select vce level based on ring/task */
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adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
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/* enable/disable VCE */
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amdgpu_dpm_powergate_vce(adev, !enable);
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mutex_unlock(&adev->pm.mutex);
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} else {
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mutex_lock(&adev->pm.mutex);
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adev->pm.dpm.vce_active = false;
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mutex_unlock(&adev->pm.mutex);
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}
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if (enable) {
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mutex_lock(&adev->pm.mutex);
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adev->pm.dpm.vce_active = true;
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/* XXX select vce level based on ring/task */
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adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
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mutex_unlock(&adev->pm.mutex);
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} else {
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mutex_lock(&adev->pm.mutex);
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adev->pm.dpm.vce_active = false;
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mutex_unlock(&adev->pm.mutex);
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}
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amdgpu_pm_compute_clocks(adev);
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amdgpu_pm_compute_clocks(adev);
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}
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}
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void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
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@ -43,6 +43,7 @@
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#include "gfx_v8_0.h"
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static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
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static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
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static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps)
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{
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@ -558,6 +559,7 @@ static int cz_dpm_late_init(void *handle)
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/* powerdown unused blocks for now */
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cz_dpm_powergate_uvd(adev, true);
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cz_dpm_powergate_vce(adev, true);
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return 0;
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}
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@ -826,16 +828,16 @@ static void cz_init_vce_limit(struct amdgpu_device *adev)
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return;
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}
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pi->vce_dpm.soft_min_clk = 0;
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pi->vce_dpm.hard_min_clk = 0;
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pi->vce_dpm.soft_min_clk = table->entries[0].ecclk;
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pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
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cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
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level = cz_get_argument(adev);
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if (level < table->count)
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clock = table->entries[level].evclk;
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clock = table->entries[level].ecclk;
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else {
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/* future BIOS would fix this error */
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DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n");
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clock = table->entries[table->count - 1].evclk;
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clock = table->entries[table->count - 1].ecclk;
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}
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pi->vce_dpm.soft_max_clk = clock;
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@ -1004,6 +1006,36 @@ static uint32_t cz_get_sclk_level(struct amdgpu_device *adev,
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return i;
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}
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static uint32_t cz_get_eclk_level(struct amdgpu_device *adev,
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uint32_t clock, uint16_t msg)
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{
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int i = 0;
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struct amdgpu_vce_clock_voltage_dependency_table *table =
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&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
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if (table->count == 0)
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return 0;
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switch (msg) {
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case PPSMC_MSG_SetEclkSoftMin:
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case PPSMC_MSG_SetEclkHardMin:
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for (i = 0; i < table->count-1; i++)
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if (clock <= table->entries[i].ecclk)
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break;
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break;
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case PPSMC_MSG_SetEclkSoftMax:
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case PPSMC_MSG_SetEclkHardMax:
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for (i = table->count - 1; i > 0; i--)
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if (clock >= table->entries[i].ecclk)
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break;
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break;
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default:
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break;
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}
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return i;
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}
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static int cz_program_bootup_state(struct amdgpu_device *adev)
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{
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struct cz_power_info *pi = cz_get_pi(adev);
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@ -1285,6 +1317,7 @@ static int cz_dpm_disable(struct amdgpu_device *adev)
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/* powerup blocks */
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cz_dpm_powergate_uvd(adev, false);
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cz_dpm_powergate_vce(adev, false);
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cz_clear_voting_clients(adev);
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cz_stop_dpm(adev);
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@ -1775,6 +1808,96 @@ static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
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}
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}
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static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
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{
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struct cz_power_info *pi = cz_get_pi(adev);
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int ret = 0;
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if (enable && pi->caps_vce_dpm) {
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pi->dpm_flags |= DPMFlags_VCE_Enabled;
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DRM_DEBUG("VCE DPM Enabled.\n");
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ret = cz_send_msg_to_smc_with_parameter(adev,
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PPSMC_MSG_EnableAllSmuFeatures, VCE_DPM_MASK);
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} else {
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pi->dpm_flags &= ~DPMFlags_VCE_Enabled;
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DRM_DEBUG("VCE DPM Stopped\n");
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ret = cz_send_msg_to_smc_with_parameter(adev,
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PPSMC_MSG_DisableAllSmuFeatures, VCE_DPM_MASK);
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}
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return ret;
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}
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static int cz_update_vce_dpm(struct amdgpu_device *adev)
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{
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struct cz_power_info *pi = cz_get_pi(adev);
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struct amdgpu_vce_clock_voltage_dependency_table *table =
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&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
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/* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
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if (pi->caps_stable_power_state) {
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pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk;
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} else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */
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pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
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}
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cz_send_msg_to_smc_with_parameter(adev,
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PPSMC_MSG_SetEclkHardMin,
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cz_get_eclk_level(adev,
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pi->vce_dpm.hard_min_clk,
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PPSMC_MSG_SetEclkHardMin));
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return 0;
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}
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static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
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{
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struct cz_power_info *pi = cz_get_pi(adev);
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if (pi->caps_vce_pg) {
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if (pi->vce_power_gated != gate) {
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if (gate) {
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/* disable clockgating so we can properly shut down the block */
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amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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/* shutdown the VCE block */
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amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_GATE);
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cz_enable_vce_dpm(adev, false);
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/* TODO: to figure out why vce can't be poweroff. */
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/* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
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pi->vce_power_gated = true;
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} else {
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cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
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pi->vce_power_gated = false;
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/* re-init the VCE block */
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amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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/* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
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amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_GATE);
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cz_update_vce_dpm(adev);
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cz_enable_vce_dpm(adev, true);
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}
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} else {
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if (! pi->vce_power_gated) {
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cz_update_vce_dpm(adev);
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}
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}
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} else { /*pi->caps_vce_pg*/
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cz_update_vce_dpm(adev);
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cz_enable_vce_dpm(adev, true);
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}
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return;
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}
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const struct amd_ip_funcs cz_dpm_ip_funcs = {
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.early_init = cz_dpm_early_init,
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.late_init = cz_dpm_late_init,
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@ -1806,6 +1929,7 @@ static const struct amdgpu_dpm_funcs cz_dpm_funcs = {
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.force_performance_level = cz_dpm_force_dpm_level,
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.vblank_too_short = NULL,
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.powergate_uvd = cz_dpm_powergate_uvd,
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.powergate_vce = cz_dpm_powergate_vce,
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};
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static void cz_dpm_set_funcs(struct amdgpu_device *adev)
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@ -1263,7 +1263,7 @@ static int vi_common_early_init(void *handle)
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case CHIP_CARRIZO:
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adev->has_uvd = true;
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adev->cg_flags = 0;
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adev->pg_flags = AMDGPU_PG_SUPPORT_UVD;
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adev->pg_flags = AMDGPU_PG_SUPPORT_UVD | AMDGPU_PG_SUPPORT_VCE;
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adev->external_rev_id = adev->rev_id + 0x1;
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if (amdgpu_smc_load_fw && smc_enabled)
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adev->firmware.smu_load = true;
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