phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register
[ Upstream commit 488987b2d5cade4e7680f7e81590435a848d1fa9 ] Change QSERDES_V5_COM_CMN_MODE to be defined to 0x1a0 rather than 0x1a4. The only user of this register name (sm8450_qmp_gen4x2_pcie_serdes_tbl) should use the 0x1a0 register, as stated in the downstream dtsi tree. Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -1116,7 +1116,8 @@
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#define QSERDES_V5_COM_CORE_CLK_EN 0x174
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#define QSERDES_V5_COM_CMN_CONFIG 0x17c
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#define QSERDES_V5_COM_CMN_MISC1 0x19c
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#define QSERDES_V5_COM_CMN_MODE 0x1a4
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#define QSERDES_V5_COM_CMN_MODE 0x1a0
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#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
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#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
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#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
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#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
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