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clk: socfpga: Fix the smplsel on Arria10 and Stratix10

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The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.

Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.

Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Dinh Nguyen 2017-06-08 09:18:39 -05:00 committed by Stephen Boyd
parent a925810f6e
commit b7f8101d6e
2 changed files with 4 additions and 1 deletions
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2
drivers/clk/socfpga/clk-gate-a10.c
View File

@ -86,7 +86,7 @@ static int socfpga_clk_prepare(struct clk_hw *hwclk)
} }
} }
hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
regmap_write(socfpgaclk->sys_mgr_base_addr, regmap_write(socfpgaclk->sys_mgr_base_addr,
SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);

3
drivers/clk/socfpga/clk.h
View File

@ -32,6 +32,9 @@
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
extern void __iomem *clk_mgr_base_addr; extern void __iomem *clk_mgr_base_addr;
extern void __iomem *clk_mgr_a10_base_addr; extern void __iomem *clk_mgr_a10_base_addr;