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cxgb4: Pass in a Congestion Channel Map to t4_sge_alloc_rxq()

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Passes a Congestion Channel Map to t4_sge_alloc_rxq()
for the Ethernet RX Queues based on the MPS Buffer Group Map
of the TX Channel rather than just the TX Channel Map.
Also, in t4_sge_alloc_rxq() for T5, setting up the
Congestion Manager values of the new RX Ethernet Queue is
done by firmware now.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hariprasad Shenai 2015-05-05 14:59:53 +05:30 committed by David S. Miller
parent 145ef8a54e
commit b8b1ae990e
3 changed files with 45 additions and 0 deletions
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35
drivers/net/ethernet/chelsio/cxgb4/sge.c
View File

@ -2551,6 +2551,41 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
&fl->bar2_qid);
refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL);
}
/* For T5 and later we attempt to set up the Congestion Manager values
* of the new RX Ethernet Queue. This should really be handled by
* firmware because it's more complex than any host driver wants to
* get involved with and it's different per chip and this is almost
* certainly wrong. Firmware would be wrong as well, but it would be
* a lot easier to fix in one place ... For now we do something very
* simple (and hopefully less wrong).
*/
if (!is_t4(adap->params.chip) && cong >= 0) {
u32 param, val;
int i;
param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
FW_PARAMS_PARAM_YZ_V(iq->cntxt_id));
if (cong == 0) {
val = CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_QUEUE_X);
} else {
val =
CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X);
for (i = 0; i < 4; i++) {
if (cong & (1 << i))
val |=
CONMCTXT_CNGCHMAP_V(1 << (i << 2));
}
}
ret = t4_set_params(adap, adap->mbox, adap->fn, 0, 1,
&param, &val);
if (ret)
dev_warn(adap->pdev_dev, "Failed to set Congestion"
" Manager Context for Ingress Queue %d: %d\n",
iq->cntxt_id, -ret);
}
return 0;
fl_nomem:

9
drivers/net/ethernet/chelsio/cxgb4/t4_values.h
View File

@ -61,6 +61,15 @@
#define SGE_TIMERREGS 6
#define TIMERREG_COUNTER0_X 0
/* Congestion Manager Definitions.
*/
#define CONMCTXT_CNGTPMODE_S 19
#define CONMCTXT_CNGTPMODE_V(x) ((x) << CONMCTXT_CNGTPMODE_S)
#define CONMCTXT_CNGCHMAP_S 0
#define CONMCTXT_CNGCHMAP_V(x) ((x) << CONMCTXT_CNGCHMAP_S)
#define CONMCTXT_CNGTPMODE_CHANNEL_X 2
#define CONMCTXT_CNGTPMODE_QUEUE_X 1
/* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
* The User Doorbells are each 128 bytes in length with a Simple Doorbell at
* offsets 8x and a Write Combining single 64-byte Egress Queue Unit

1
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
View File

@ -1123,6 +1123,7 @@ enum fw_params_param_dmaq {
FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
};
enum fw_params_param_dev_diag {